Tool Talk: Will 3D chips challenge SoCs?

There are many advantages to building chips "up" rather than "out," according to ISPD presenters. Making an analogy to Manhattan skyscrapers, IBM's Robert Montoye noted that with cities and ICs alike, the fastest way to add bandwidth is to go up. There are various ways to do that with ICs, ranging from two dice stacked into a single package to truly 3-D, multilayer "vertical VLSI" packages that operate like a single piece of silicon.

Going vertical, as opposed to across chips, means shorter interconnects, less power and more speed. Three-dimensional schemes can produce huge bandwidth advantages, according to Montoye. "We need more storage and more capacity, and we need to get off the main die because it's too expensive to put it on the main die," he said.

Rafael Reif, professor of electrical engineering at the Massachusetts Institute of Technology (MIT), made an interesting point as he presented MIT's work with 3-D ICs. Why cram analog and digital circuits onto a single die and then wrestle with signal isolation? Why not, instead, put separate analog and digital "layers" in a vertical 3-D stack?

One limiting factor for 3-D chips is a lack of EDA tools. MIT developed its own tools for 3-D placement and routing, design rule checking and layout management.

There are still problems to resolve with 3-D chips, such as heat removal. There may be practical issues that make them unfeasible. But they do raise an interesting question: Are we so accustomed to thinking about chip design in two dimensions that we've ignored something obvious?

The real message to the EDA community is that systems-on-chip, as envisioned, aren't the only game in town. It would be a mistake to assume that designers will put all their functionality on one die just because the process technology theoretically allows it.

There may be better, faster and cheaper ways to get complicated systems out the door. EDA vendors should weigh the options and not put all their eggs in the SoC basket.