EETimes' Industry Challenge: Assessing the structured-ASIC alternative

The best way to examine the costs of a structured ASIC is in comparison with the costs of a cell-based design. Most of the differences come from the fact that the base wafer, which contains all of the hard design work and critical fabrication steps, is the same for every customer. So the most expensive part of the design is amortized over the whole life of a structured-ASIC family, instead of being extracted from one customer.

That means, in the first place, that nonrecurring engineering charges (NREs) can be significantly lower than would be required on the same level of cell-based design. The ASIC vendor is doing less design work and ordering only a few masks. Depending on the complexity of the ASIC family, NREs as low as $25k to $50k are feasible. Comparison with a customer-owned-tooling design is similarly favorable, since few masks are being ordered and no shuttle runs are necessary to produce the wafers.

Structured ASICs generally do not require the design team to use special tools, although the ASIC vendor may use highly specialized in-house tools. Generally, intellectual property for structured-ASIC designs will come from the ASIC vendor as well, eliminating issues about third-party IP licenses.

Unit prices on production chips may be quite comparable to cell-based ASICs. Structured ASICs are inherently slightly less dense than cell-based ASICs in the same process, because of more conservative placement and routing rules, as well as the inefficiencies of the logic fabric and of the fixed resources. So the actual silicon-related costs may be slightly higher for structured ASICs. But since the base wafer design cost, inventory costs and risks are amortized across all customers for a given family of structured ASICs, not just one particular design, the amortization portion of the piece price is reduced. The result is often a lower piece price for the structured device.

Such streamlining is possible because a number of features that have to be inserted into cell-based netlists already exist in the structured ASIC, woven into the device's fabric. These include power and ground grids, clock networks and scan chains. The good news is that the design team doesn't need to spend resources inserting these things into most structured-ASIC architectures. The bad news, of course, is that they are done to the vendor's standards, not the design team's. Since power and clock networks have to be designed for worst-case conditions, it is usually not possible in a structured ASIC to optimize them; you just use what's there. Similarly, scan structures will follow the vendor's concept of design-for-test, not necessarily the customer's.

There is another important side to this issue, however. Particularly in 130 nanometers, signal-integrity analysis and supply-grid stability are important steps in the design process for cell-based designs. While those may be done by the vendor, they still have to be done for each iteration of the design. Structured ASICs, in contrast, generally use more restrictive routing rules and heavier supply metal, so that an a priori analysis of voltage droop and signal integrity for the base wafer will suffice. These delicate analyses don't have to be repeated for each customer design.

Finally there is the matter of fab turnaround time. Since only a few top layers of the wafer are being created for the design, mask shop and fab time is minimized. Often, structured-ASIC vendors do the metal-stack work in their own facilities, so an offshore foundry isn't even involved.

That reduces the turnaround time for samples-and, more critically, for respins-from months to weeks. This advantage, by itself, has led some design teams to consider structured ASICs as at-speed prototyping tools for cell-based system-on-chip designs.

There are new risks, however. One is design fit. The structured-ASIC fabric is fixed, and the diffused blocks for memory, serializer/deserializer, etc., are also immutable. Maximum core operating frequencies (as opposed to maximum best-case clock frequencies, which can be much higher) are typically lower than would be the case for a leading-edge cell-based design in the same geometry. Typical frequencies for 180-nm and 130-nm structured ASICs are in the 200- to 300-MHz range.

This makes it possible for a design to simply overrun the resources available in a given structured-ASIC family. The design may require too much embedded SRAM or demand too much performance or simply need too much fast I/O. Since the opportunities to use aggressive power-management strategies-such as clock gating, power throttling and so forth-are limited in structured-ASIC families, the devices may not be able to meet stringent power requirements, though they certainly will do far better than similar-capacity FPGAs. All of those factors are known at the beginning of the design, but they deserve attention if preliminary analysis suggests that the design will be close to the limits of a structured-ASIC family.

Some risks are less tangible. The relationship between vendor and design team on a structured-ASIC design is similar to that in a cell-based design, but it is not identical.

The significance of the limitations imposed by the structured architecture of the base wafer may be difficult to analyze for a particular design, especially if the design pushes the envelope. And the concept is relatively new.

All of those factors have led some design managers to take a wait-and-see approach, finding other alternatives until there is a body of public experience on structured-ASIC application.

Finally, there is the risk of vendor failure. Some of the structured-ASIC vendors are small fabless companies. Given the degree to which the design team is dependent on the structured-ASIC vendor, it behooves the team to investigate the vendor's stability.

On the reward side, structured ASICs offer a substantial portion of the capacity, performance and energy efficiency of cell-based design, but with a lower NRE, a simplified design flow and a faster turnaround time. In this regard they occupy an important space between the simplest cell-based designs and the most powerful FPGA applications.

See related chart