Virtual Silicon Cuts Leakage 250X With Mobilize
First Power Management IP Solution Extends Moores Law into the Nanometer Era Sunnyvale, CA - July 12, 2004 -
Virtual Silicon Technology, Inc., a leader in semiconductor intellectual property, today introduced Mobilize(TM), the industrys first complete power management intellectual property (IP) platform to reduce dynamic and static (leakage) power of systems on chip (SoC). Mobilize is targeted to help SoC designers working in the battery-powered, mobile application space to manage power more effectively, thereby extending Moore's law beyond the power barriers at 130nm process technology and below.>
The Mobilize Power Management IP platform provides an adaptive, dynamically configurable solution for reducing both static and dynamic power in 130nm SoC. Virtual Silicons patented Gate Bias(TM) technology is the key element within Mobilize. In gate biasing, the leakage of the cell is reduced by over 250X on a standard 130nm process (generic) with no sacrifice to the performance of the SoC.
Gate Bias includes data retention flip-flops so there is no loss of state during the leakage reduction mode. As a result, Gate Bias can be turned on and off in as little as 20ns, allowing designers greater flexibility to implement leakage reduction.
"Virtual Silicons Mobilize is the first and only commercially available solution to resolve the power crisis at 130nm and 90nm without compromising performance or cost," said Barry Hoberman, president and CEO of Virtual Silicon. "The combination of Mobilize-enabled foundation IP with higher level, power management IP offers processor-based designers significant architectural opportunities for reducing leakage."
Customer analysis has shown that Gate Bias technology can reduce the leakage of a 1 million-gate power island from 2.21 milliamps to just 8.3 microamps. In addition to cutting leakage, Mobilize reduces the dynamic power of an SoC by potentially more than 80 percent through the use of dynamic voltage and frequency scaling.
Virtual Silicons Mobilize IP continues the collaboration between Virtual Silicon and National Semiconductor Corp. on PowerWise(R) technology. "Our PowerWise technology is enabling SoC designers to greatly extend the battery life of portable devices. The unique capabilities of Mobilize power management IP by Virtual Silicon, a PowerWise Interface (PWI) adopter, places a powerful tool in the hands of SoC designers.", said Peter Henry, vice president of portable power systems.
Mobilize is endorsed by leading foundries, EDA companies, power management integrated circuits suppliers and IP companies. Virtual Silicon further disclosed that initial customers are actively designing SoC with Mobilize IP and anticipate end-of-year design tape-outs.
The complete 130nm process technology Mobilize IP platform is currently available for license download on the Virtual Silicon website (http://www.virtual-silicon.com). All IP elements are tape-out ready, so designers can start using Mobilize immediately to save power on their current SoC designs. A full test chip report for 130nm will be available in September 2004. The 90nm Mobilize Power Management IP platform will be tape-out ready in 1Q05. Mobilize, Gate Bias, Your Source for IP, VIP, Silicon Ready, The Heart of Great Silicon and Virtual Silicon are trademarks of Virtual Silicon Technology, Inc.
Synopsys: Bijan Kiani, vice president of marketing, Synopsys Implementation Group "At 90 nanometers and below, the need for superior dynamic and leakage power reduction has become mission-critical for power-efficient design," said Bijan Kiani, vice president of marketing, Synopsys Implementation Group. "Pairing Synopsys' Galaxy Power with Virtual Silicons Mobilize IP benefits our mutual customer base by providing an advanced low power solution for implementing techniques such as power islands and gate biasing in their latest SoC designs."
In-Stat MDR: Gerald S. (Jerry) Worchel, principal analyst. "With our world rapidly moving more and more into the mobile (or portable) space, battery life or product power dissipation have become of increasingly higher concern. In large part, this power issue is the result of rapidly increasing leakage currents at and below the 130-nanometer node. This announcement by Virtual Silicon presents their approach to power management, which will be one of the keys to IC, product, and hence, company success in the future."
Cadence: "Power has become a key concern in nanometer silicon," said Eric Filseth, vice president of product marketing for the Cadence Encounter" digital IC design platform. "Cadence and Virtual Silicon collaborated to integrate the Mobilize IP into the Encounter platform's low-power design flow. This solution helps our customers implement aggressive low-power strategies quickly, even on very large SoC."
MoSys: Dr. Fu-Chieh Hsu, president and CEO, MoSys is addressing the requirements of SoC designers to reduce power consumption in the latest generation processes while minimizing chip cost with our innovative 1T-SRAM-M(TM) and 6T-SRAM-R(TM) memory technologies. We are pleased to partner with Virtual Silicons Mobilize Power Management IP to offer customers a complete power-optimized solution."
Magma: Vess Johnson, general manager of Magma's Silicon Correlation Division, said, "In addressing our customers' power characterization and modeling needs, Silicon Correlation Division has seen the high performance, low power design challenge spawn a myriad of new design techniques. The Mobilize platform is one of the most compelling solutions for reducing static and dynamic power I have seen."
Tensilica: Chris Rowen, president and CEO, "Configurable processors offer silicon designers order-of-magnitude improvements in energy efficiency over conventional processor cores," stated Chris Rowen, president and CEO of Tensilica, Inc. "We have worked with Virtual Silicon to take 32-bit high-performance processor power efficiency even further. We conducted a benchmark of our Xtensa processor with the new PowerSaver(TM) library and we were very impressed with the results. Compared to 1.2V, Virtual Silicons 1.0V library achieved a 17% typical power reduction and the 0.8V library achieved a 53% power reduction at the same post-layout speed for a small Xtensa LX core. At 150MHz, the 0.8v core power dissipation was less than 3.8mW, simulated from the actual layout."
About Virtual Silicon Technology
Virtual Silicon is a leading supplier of semiconductor intellectual property and process technology to manufacturers and designers of complex systems-on-chip (SoC). Headquartered in Sunnyvale, CA, the company provides process-specific embedded components that serve the wireless, networking, graphics, communication and computing markets. Customers include leading fabless semiconductor companies, integrated semiconductor manufacturers, foundries, and SoC developers who demand leading edge technology for their semiconductor innovations. For more information, call (408) 548-2700 or visit Virtual Silicon online at www.virtual-silicon.com.
Copyright © 2004, Virtual Silicon Technology Inc. All rights reserved.
Mobilize, Gate Bias, Your Source for IP®, Silicon Ready, The Heart of Great Silicon® and Virtual Silicon are trademarks of Virtual Silicon Technology, Inc.
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