Paxonet announces industry's largest IP core portfolio for data and telecomunications

All Cores Re-targetable In FPGA, Structured And Traditional ASIC Implementations, Further Enabling Fast Time to Design and Market

Fremont, CA— September 22, 2004 — Paxonet Communications, Inc, can now boast the industry’s largest collection of verifiable and proven IP cores, numbering more than 75, for data and telecommunications. Most of these cores are supported with evaluation boards and software drivers. With the ongoing building of its IP core portfolio, design services and customizable chip and board development, Paxonet can claim to provide a complete, design and development solution.
Systems designers and semiconductor vendors targeting networking and communications vendors can now integrate all the necessary logic from a single source through a myriad of implementations for a variety of processes.

All cores are re-targetable for design and implementation in FPGA  (Altera and Xilinx), structured ASIC and cell-based ASIC methodologies in technologies ranging from 0.25um to 90nm and below.

The company’s IP portfolio ranges from SONET/SDH (155Mbps to 10Gbps), Ethernet (10 Mbps to 10 Gbps), PDH, Layer 2 processing, virtual concatenation and GFP. These new IP cores are complete, comprehensive and ready for design-in.  

Another first for the industry, Paxonet offers three standard variations of virtual concatenation technology.  The first of these is HOVC-only (CC375 and CC377 for STS48/STM16 and CC475 STS192/STM64) for connecting Gigabit Ethernet, FibreChannel or similar networking protocols to high-speed SONET and SDH pipes. 

The second is a LOVC-only (CC376 for STS3/STM1 and STS12/STM4) version that is ideal for transport of 10/100 Ethernet in a mixed voice/data environment. 

The third variant is a combined HOVC and LOVC for STS48/STM16 highly integrated, aggregation applications. All these designs implement LCAS, so that bandwidth can be flexibly added and dropped from bundles as demanded by customer bandwidth needs or by network reconfigurations.

“All of our cores are modular in structure and designed to meet our customer’s needs regarding volume, cost, feature set, performance and power management,” said Y.N. Kumar, vice president of Technology and Strategic Programs for Paxonet. 

“If design and integration expertise is not resident in-house, we also offer design and support services that help our customers create feature rich products with dramatically reduced development costs and time to market,” Mr. Kumar added. 

These IP cores are the result of many years of ASIC/FPGA and system development experience.  They are all designed for interoperability so that our customers can get a complete solution from a single source ensuring minimal integration problems, a key factor in designing a new chip or equipment.

Evaluation boards are available for most of these cores.  In addition and as always, Paxonet will customize these cores for individual customers. Paxonet can provide cores ready to use in any FPGA technology, or retarget them toward the customer’s ASIC implementation of choice.

The company provides cost-effective specification-to-GDSII design services, to support implementation in FPGA or COT/ASIC technologies.
   
About Paxonet

Paxonet Communications Inc. is a comprehensive design and intellectual property company offering design services, the industry’s widest range of networking and communications cores, and customized board and chip design.  Applications include all aspects of data and telecommunications, home networking and consumer communications electronics. The company is privately held and employs 115 people.  Please visit http://www.Paxonet.com for more information.

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