Adaptive Silicon claims to cut cost of embedded programmable logic in SoC designs

Adaptive Silicon claims to cut cost of embedded programmable logic in SoC designs
By Semiconductor Business News
March 12, 2001 (1:22 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010312S0081

MUNICH -- What's best--embedding chunks of programmable logic in large system-on-chip (SoC) designs, or integrating standard functions in large programmable logic devices?

Privately-held Adaptive Silicon Inc., founded by former managers from National Semiconductor Corp., believes embedded programmable logic in multi-million-gate ASICs and standard ICs is the best way to go. Aiming to make it even better, the Silicon Valley startup today (March 12) unveiled its Multi-Scale Array (MSA) architecture, which the company says it the first commercially available intellectual property (IP) for embedded programmable logic.

The MSA architecture is made up of two parts--"hard" intellectual property, consisting of configurable 4-bit arithmetic logic units, and "soft" IP for interfacing the blocks of ALUs to other functions. The 4-bit ALUs are grouped together in fours, called "Quad Blocks." These blocks are then used to build up fine-grain programmable logi c functions, or "Hex Blocks." The "soft" IP is used to create interfaces to on-chip buses, testers, and programmable structures.

The technology was formally introduced today at the Design, Automation, and Test in Europe (DATE) conference in Munich, and it's now available for licensing by fabless chip houses, ASIC suppliers, and integrated device manufacturers (IDMs).

LSI Logic Corp., an investor in the startup, has licensed the MSA architecture, and it has produced functional blocks in test chips using its 0.18-micron CMOS technology. Test chips are also expected to be produced in the second quarter by Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Other licensing pacts are planned with foundries and chip houses in 2001, said Ralph Zak, vice president of marketing at Adaptive Silicon in Los Gatos, Calif.

"We are seeing an emerging battle between programmable logic suppliers trying to become more system-level oriented with standard functions in their products and the ASIC companies trying to add programmable logic to their designs," Zak noted. "You can think of it as 'big' programmable logic, small number of standard cell functions vs. big standard cell, little programmable logic [blocks]," he said.

"We are enabling the standard parts people and ASIC vendors to add small amounts of programmable logic to what otherwise would be fixed function parts," Zak added.

Do do that, Adaptive Silicon is focusing exclusively on embedded programmable logic for chip designs. The company's Multi-Scale Array of ALUs and "soft" adapters are intended to reduce the space and price of programmable logic in designs. Traditional programmable logic devices are built with arrays of lookup tables that require more silicon space. Adaptive Silicon has also built in self-test functions that speed the testing time to less than a millisecond to further reduce the cost of using embedded programmable logic in ASICs and standard ICs, Zak said.

"You can look at the [MSA] as an array of ALUs, which are micro-programmed , or as bit slices, which are treated as an array of logic elements. This is designed to make it equally efficient in random logic or control logic applications," said the marketing vice president.

The control function in SoC and large ASIC designs is often considered the highest risk, "especially when multiple processors are used on a chip," Zak said. The MSA-based IP core can also work as a field-programmable logic block for algorithms-such as encryption--that might change or be upgraded periodically, he said.

For chip companies working on multi-million-gate ICs, the use of programmable logic can help to reduce development risks by enabling changes after parts are made. The cost of new mask sets alone is driving this movement, Zak said. "It costs $300,000 to $400,000 for masks at 0.18 micron, and three-quarters of a million dollars at 0.13-micron. We've been told that 0.10-micron designs could have mask costs of $1 million," he added.

Chip house could also use embedded programmable logic to qui ckly tailor basic product designs for key market segments or specific customers instead of spinning out new iterations and mask sets, Zak suggested.

The MSA 2500 Programmable Logic Core comes with a complete series of software tools, called Millennium PLC. This includes a set of optimized synthesis libraries for register transfer language (RTL) using tools Synopsys Inc.'s Design Compiler engine. (Synopsys is also an investor in Adaptive Silicon.)

Adaptive Silicon is licensing its technology in two parts. One set of licensing agreements covers design use, based on the number of products developed. Companies producing one or two designs with the MSA technology will pay $450,000, while a higher number of designs will bring that amount down to about $300,000 per design, Zak said.

For production, Adaptive Silicon is offering a per-Hex Block royalty. The cost could be as low as $0.18 per Hex Block with a minimum charge of $50,000 per years. Licenses for the Millennium PLC software starts at $50,000 for one year (single-user for one architecture and one process). An additional $20,0000 is charged for additional architectures and $10,000 for additional processes.

--By J. Robert Linebackreporting from the U.S.