Startup claims breakthrough in SoC routing

Startup claims breakthrough in SoC routing
By Richard Goering, EE Times
March 5, 2001 (2:19 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010305S0079

SAN JOSE, Calif. — Claiming a fresh approach to routing complex systems-on-chip (SoCs), startup Plato Design Systems will announce its mission this week. The company plans to roll out this spring a router that claims a tenfold performance and capacity gain over existing tools, while offering concurrent routing, 3-D extraction, analysis and optimization for timing and signal integrity.

President and chief executive officer Limin He and vice president of R&D David Yao founded Plato in 1999. He formerly managed Cadence Design Systems' placement and routing group and was a developer of that company's QPlace technology. Yao was involved in placement and routing development at CLK CAD, Arcadia Design Systems and Mentor Graphics.

Joe Xi, Plato vice president of marketing, recently left a similar position at Ultima Interconnect Technology to join Plato. The new company has $2.2 million in venture funding fr om Acorn Angels, a group of Silicon Valley executives.

"There have been a lot of enhancements in the unification of synthesis and placement, but routing is the bottleneck," said He. "Right now, we feel that routing is the place that needs a revolutionary solution."

"We consider ourselves to be the first company that can provide scalable technology in performance and capacity for routing large SoC designs," said Xi. "By scalable, we mean that run-time performance and capacity can stay within the increase of design complexity." By using parallel processing, Plato said, it can handle up to 20 million gates flat.

What's more, Plato claims breakthrough technology with its concurrent routing, extraction and analysis solution. Even with the current emphasis on physical synthesis, that's important, Xi said. "Only at the routing stage can interconnect be accurately determined and controlled," he noted.

Xi said that Plato will field a single router that can handle both top-level and detailed cell-level routing. Thus, in theory, a user of a physical synthesis tool like Synopsys' Physical Compiler might need only Plato's product to finish the job. However, Plato's initial solution focuses on signal nets, so additional clock and power routers may be needed.

'Graph-based' tool

Plato's upcoming router will be a "graph-based" router, a term the company is so far declining to define. Xi said the concept is closer to that of a gridded router than a shape-based router, but that Plato's graph-based router will have "almost the same" flexibility as a shape-based router for dealing with off-grid pins, wide wires and wide spacing. It will also be faster than today's gridded routers, even for a single-CPU solution, he said.

It's the parallel processing, however, that allows Plato's router to deal with really big chips. Xi claimed that run-time performance is "almost linear" as more CPUs are added.

According to company benchmark data, a 250-MHz Sun Enterprise 4000 with 10 CPUs was able to rout e a 505,000-cell design with 501,000 nets in 19 minutes. With two CPUs, Plato's solution routed a 331,000-cell design with 157,000 nets in 22 minutes.

These times are for routing only. Xi said that online extraction, analysis and optimization adds only a 5 percent overhead on top of routing speeds.

Plato claims to run an online, 3-D resistance-capacitance (RC) extraction as routes are laid. That can be done for critical nets or for all nets, according to user request. Three-dimensional extraction is conventionally very slow, and Plato isn't releasing details about how the company handles that problem. Xi noted, however, that the router has geometric information available to it and doesn't need to read in an entire layout and decompose the geometry. "I wouldn't call it a library, but we do have 3-D structures we use to build the models," he said.

Following extraction, the Plato solution runs delay calculation and static timing analysis. In the optimization stage, it fixes routes to meet the user's timing and cross-coupling constraints.

Plato's solution is aimed at ASIC designs in a variety of applications areas. At present, the company said, evaluations are under way at two networking companies, three graphics companies, two large ASIC companies, one consumer electronics company and one microprocessor provider. Plato also said that a networking company will tape out a 7-million-gate ASIC using its solution in March. Plato declined to name any customers, however.

To tie in to existing EDA vendor tools, Plato's solution will read standard file formats such as LEF, DEF, SDF, DSPF and the Synopsys ".lib" libraries.

The 10-person startup is currently setting up a marketing and distribution channel. Further product details are expected in April.