TransEDA Code Coverage Tool Integrated with Verisity's vManager to Boost Verification Productivity for Mixed-Language Designs

TransEDA VN-Cover Integration Provides Both Verilog and VHDL Coverage

MOUNTAIN VIEW, Calif. & EASTLEIGH, United Kingdom--(BUSINESS WIRE)--Nov. 3, 2004 -- Verisity Ltd. (Nasdaq:VRST), the leading supplier of Verification Process Automation (VPA) solutions, and TransEDA, a leader in coverage and ready-to-use verification solutions, jointly announce the introduction of a powerful integration between vManager(TM) and VN-Cover.

VN-Cover is a comprehensive code and FSM coverage solution that identifies unverified portions of simulated HDL designs. One of the tool's strengths includes the ability to deliver vendor-neutral coverage across simulators, languages, and platforms. In addition, its unique "deglitch" and "coverability analysis" capabilities enable the industry's highest accuracy for coverage measurement. By integrating with Verisity's vManager, the industry's first project-level verification management system, the companies will now offer a project-wide solution for combining all sources of coverage from specification to closure.

The VN-Cover integration follows a recent integration of TransEDA's specification coverage tool, VN-Spec. VN-Spec fills a gap in front-end verification by tying original specification documents to both implementation and verification flows, using requirement traceability graphs to define specification coverage metrics.

"The two companies can now claim a fully automated coverage flow," said Steve Brown, Director of Channel Marketing for Verisity. "This integration provides evidence of how vManager's completely unique project-level capabilities are being embraced by partners and customers."

The TransEDA VN-Cover integration enables Verilog, VHDL and mixed-language code coverage to be collected and used for project-level verification by a greater number of engineers. The new VN-Cover integration completes total coverage measurement with mixed-language code coverage, in addition to functional coverage provided by Verisity's Specman Elite(TM) and assertion coverage of PSL, OVL and Checkerware. Code coverage data in Verilog and/or VHDL is collected during simulation runs and imported to vManager for analysis, display, and reporting of the integrated total coverage model and project management.

"We anticipate our mutual customers will immediately recognize the importance of this solution because it promises to have a significant impact on productivity," said Modesto Casas, head of Worldwide Marketing at TransEDA. "By automatically connecting these tools and the information that flows between them, the engineering community gets a brand new verification closure solution to deploy on complex designs."

About TransEDA

TransEDA is a leader in coverage and ready-to-use verification solutions for electronic designs. The company has over ten years of operating experience in the EDA market. TransEDA provides advanced verification products for simulation platforms including coverability analysis capability, specification coverage and impact analysis, configurable HDL rule checking, static assertion verification, static bus controller coverage, verification IP, bus-based system-level test automation, test suite optimization, and transistor-level functional abstraction. TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, and local representatives in China, India, Korea, Singapore and Taiwan. For more information, visit www.transeda.com.

About Verisity

Verisity Ltd. (Nasdaq:VRST) is the leading supplier of process automation solutions for the functional verification market. The Company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing and consumer electronics global markets. Verisity's VPA solutions enable projects to move from executable verification plans to unit, chip/system and project level "total coverage" and verification closure, while maximizing productivity, product quality and predictability of schedules. The Company's strong market presence is driven by its proven technology, methodology and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. For more information, visit www.verisity.com.

Verisity, the Verisity logo, Specman Elite, and vManager are either registered trademarks or trademarks of Verisity Design, Inc., in the United States and/or other jurisdictions. TransEDA, the TransEDA logo, Verification from Concept to Reality, Verification Navigator, VN-Cover and VN-Spec are registered trademarks of TransEDA Technology Inc. All other trademarks are the property of their respective holders.

SOURCE: Verisity Ltd.

"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Statements in this press release regarding Verisity's business which are not historical facts are "forward-looking statements" that involve risks and uncertainties. For a discussion of such risks and uncertainties, which could cause actual results to differ from those contained in the forward-looking statements, see "Risk Factors" in the Company's Annual Report or Form 10-K for the most recently ended fiscal year.