Programmable logic takes tough step into ASICs

Programmable logic takes tough step into ASICs
By Anthony Cataldo, EE Times
February 16, 2001 (10:29 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010215S0047

MONTEREY, Calif. — Hybrid ASICs with programmable logic cores are about to get their first big break as Actel Corp. seeds leading foundries with programmable logic cores and as LSI Logic Corp. gears up to manufacture its first ASIC/PLD hybrids early this year.

The benefit of adding on-the-fly programmability to otherwise fixed-function chips is clear: flexible systems-on-chip with sufficient wiggle room to allow changes — say, to an I/O interface — after a part has been fabbed. One compelling denouement of the exercise could be the creation of a class of system-on-chip platforms that could be deployed across multiple products.

But hurdles remain to be cleared before that goal is attained. They include logic density penalties, meager logic performance and high power consumption, according to a panel of experts speaking here at this week's FPGA 2001 conference.

"The question," said Actel president and chief executive officer Jo hn East, "is how you get programmability without defeating the very reason you go with ASICs in the first place."

Actel (Sunnyvale, Calif.) appears willing to pursue the answer. This week, the company announced it had licensed a set of FPGA cores, called Varicores, to foundries Chartered Semiconductor, Taiwan Semiconductor Manufacturing Co. and United Microelectronics Corp. East, who earned his stripes while working at Fairchild Semiconductor in the 1960s, said the move to embedded programmable cores might be bumpy but is as inevitable as the move to CMOS was in the 1970s.

"CMOS was well-understood and seen as inevitable. But it was too tough to make the n channel, the die size was big and the yield was low," he reminded conference attendees.

East isn't alone in his thinking. Another company whose founder is a Fairchild alumnus — LSI Logic Corp. (Milpitas, Calif.) — has folded programmable logic cores developed by partner Adaptive Silicon Inc. (Los Gatos, Calif.) into its ASIC process. So far, it has received orders from about half a dozen customers for the hybrid chips, and the company expects to ship the devices in the second quarter, said Peter Gasperini, LSI Logic's ASIC product marketing manager.

As the first orders come through, Adaptive Silicon is expected to articulate its road map next month. Adaptive Silicon's president and chief operating officer, Tim Garverick, hinted that Synopsys Inc. and Synplicity Inc. — both investors in Adaptive Silicon — plan synthesis tools specific to the company's embedded programmable cores. Synthesis is one area that LSI Logic has indicated could use some streamlining.

The notion of embedding programmable logic cores into standard-cell ASICs has been bandied about for roughly four years, but progress has been stymied by the unpalatable prospects of bolting slow and fat programmable logic cores next to ASIC cells optimized for speed and density. Now Actel, Adaptive Silicon and others say they are narrowing the density and performa nce gap.

Late alterations

If they succeed in that endeavor to designers' satisfaction, the market could see the arrival systems-on-chip that could be altered after fabrication. Actel, for one, thinks the capability could apply to any device with a microcontroller or digital signal processor.

More important, it could lead to SoC platforms that are applicable across multiple products. The designer of an LCD controller for a printer, for example, would be able to designate an area where the printer head drivers could be programmed after production, thus making the device as applicable to a copier as to a printer, said Yankin Tanurhan, director of Actel's embedded FPGA program.

"We're helping shield ASIC and ASSP suppliers against market shifts," Tanurhan said.

Indeed, some see little choice but to move to reconfigurable SoC platforms because the spiraling nonrecurring engineering charges and other costs of designing and debugging complex, multimillion-gate ASICs are having a chil ling effect. "We're already seeing a decline in the number of ASIC starts for a given year," said Adaptive's Garverick.

The approach taken by Actel and Adaptive is to offer scalable programmable logic cores. Adaptive said its customers can integrate between 1,500 and 25,000 programmable ASIC gates, which are configurable at the gate and register-transfer levels. Actel's programmable cores range from 5,000 to 40,000 ASIC gates.

Actel's cores comprise 2,500-gate building blocks based on a three-input lookup table structure. The largest 4 x4 array includes 4,096 registers, 8,194 lookup tables, 640 I/Os and RAM modules. Actel offers five Varicore configurations — 4 x 4, 4 x 2, 4 x 1, 2 x 2 and 2 x 1 — which vary by layout and gate count.

Actel said it designed the arrays to consume a minimal die area. At 0.18 micron, the Varicore array consumes about 2,000 ASIC gates/mm², or about one-third the die area and power of a typical field-programmable gate array.

Die area compar isons

Compared with typical ASIC logic densities, a Varicore takes up about 10 times more area for a given process technology. But Actel executives noted that ASIC gates are typically 50 to 100 times more dense than standard FPGA blocks.

Garverick said Adaptive Silicon's programmable cores can also get to within 10 times the density of ASIC gates for register-intensive functions that require heavy use of flip-flops. "In our case, the basic building block can be done in two ways: as a truth table, as with a traditional FPGA array, or as an array of 4-bit ALUs. You can get closer to 10x if it's pure random logic. We think there's validity in both views."

The gate densities of the embedded FPGAs may indeed be better than discrete devices, but many observers said the arrays still have a long way to go. Scott Hauck, an associate professor of electrical engineering at the University of Washington, argued that it's not enough just to plunk down standard programmable "tiles"; users should be abl e to reconfigure the innards of the tiles themselves.

"What we need is a Tensilica of FPGAs," said Hauck, referring to the reconfigurable processor company. "We like post-silicon customization, but we want a 2x to 4x [density penalty] rather than the 10 to 100 with predefined tiles. Yes, there will be FPGA-plus-SoC, but we need to optimize for the domain of that SoC."

Intel Fellow David Papworth, who was the lead architect for Intel Corp.'s Pentium Pro processor, expressed more skepticism, saying that the low density, low performance and high cost of FPGAs will confine them to prototyping and low-volume production for the foreseeable future. "A 40-MHz processor at 0.18 micron does not impress me," he said.

Still, LSI Logic's Gasperini said one of the company's customers is using an embedded PLD core as a digital signal coprocessor commissioned for such "mundane" tasks as Viterbi decoding. Other customers are using the PLD tiles as direct memory access controllers or configurable protocol interfac es, Gasperini said.

Actel's Varicore, for its part, can reach clock speeds of 250 MHz and consumes 240 milliwatts at 100 MHz and 80 percent utilization. To reduce the size of the programmable logic blocks, the company cut back on routing resources. The cores run 20 percent slower than Xilinx Inc.'s high-end VirtexE FPGAs, said Tanurhan.

Both Actel and LSI Logic said their cores can be folded into standard RTL-based ASIC flows. Gasperini said the Adaptive Silicon cores have already been blended into LSI Logic's ASIC environment and are treated like any standard cell. "This core has to be like another piece of ASIC intellectual property," Gasperini said.

Special attention

The cores do still require some special attention in the areas of partitioning, synthesis, integration and floor planning, according to LSI Logic. But some of those areas may be addressed by tools that are expected to be announced soon.

Actel has proposed two ASIC-compatible design flows for its Varicore line. The functional flow includes RTL coding, synthesis, place and route and verification; the hard-core integration involves the GDSII block, test generation and physical verification. Actel is providing Windows NT and Unix-based compilers. The design flow supports synthesis tools from Synopsys and physical design tools from Cadence Design Systems Inc. and Avanti Corp.

Few observers here doubt that hybrid FPGAs-cum-ASICs will appear. Whether designers will tolerate the trade-offs remains open for debate.