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Silterra Adopts HPL Technologies TechXpress IP to Accelerate Development for 0.13um CMOS Process
Silterra demonstrates functional new SRAMs in just 4.5 months
KULIM, MALAYSIA and SAN JOSE, CA, January 17, 2005 - Silterra Malaysia Sdn. Bhd. and HPL Technologies, Inc. (OTC:HPLA.PK) announced today that their collaborative work has been instrumental in reducing the development and debug time for Silterra's new 0.13um CMOS process technology.
Exercising Silterra's proprietary bitcell in HPL's TechXpressT TDSRAM, Silterra was able to shorten its test vehicle development cycle time down to mere weeks and debug its initial 0.13um CMOS process, speeding its success of achieving functional 4Mb and 8Mb SRAMs.
As part of the collaboration between the two companies, Silterra licensed HPL's TechXpress IP, which was customized to Silterra's design rules and proprietary bitcells. HPL's Dallas-based test lab also provided test services and assisted Silterra in analyzing and debugging initial wafers in the new process, using the unique programmed yield signatures available in the TDSRAM.
"TechXpress IP provided excellent insight into our process capabilities and helped our engineers quickly pinpoint bottlenecks," said Bruce Gray, president and interim CEO of Silterra. "We were able to achieve working SRAMs ahead of an aggressive schedule because this test vehicle is robust enough to handle the process variations that occur early in technology development stages."
Cary Vandenberg, president and CEO of HPL Technologies, said, "Silterra leveraged our extensive TechXpress IP track record to bring 0.13um CMOS process technology to market in a fast and cost-effective manner. We are excited to be part of their success."
The TechXpress TDSRAM is part of HPL's family of array-based IP test chips for technology development, characterization and manufacturing monitoring. The TDSRAM provides a robust SRAM test circuit architecture that employs a heterogeneous bitcell array for maximum yield learning. Applications include bitcell development, design-rule evaluation, early yield ramp, burn-in, qualification and defect-density extraction. Coupled with HPL's TestChip AdvantageT software, the TDSRAM can provide quick and clear by-layer and by-location yield learning results. It has been used successfully over 30 times to characterize and accelerate the introduction of advanced technology nodes and optimize the yield ramp of these new processes.
Silterra plans to offer its 0.13um design kit in the second quarter and start pilot production in the third quarter of this year.
HPL Technologies' TechXpress TDSRAM is available now.
About Silterra Malaysia Sdn. Bhd.
Silterra Malaysia Sdn. Bhd. is a leading semiconductor wafer foundry that provides advanced foundry standard CMOS logic, high-voltage and mixed-signal/RF technologies. The company's wafer fab has a designed capacity of 40,000 eight-inch wafers per month. Silterra, which is committed to world-class service and environmental friendliness, received Notable Mention in the Malaysian Prime Minister's Hibiscus Award competition for Environmental Performance in 2003. The company is ISO 9001:2000 and ISO 14001 certified. Silterra's headquarters and factory are located in Kulim, Malaysia, and has offices in San Jose (California), Scottsdale (Arizona), Hsinchu (Taiwan) and Munich (Germany). For additional information on Silterra or its services, please visit www.silterra.com.
About HPL Technologies
HPL Technologies, Inc. is a provider of yield optimization solutions for the semiconductor and flat panel display industries. HPL offers a comprehensive portfolio of products and services including: silicon-proven intellectual property (IP), highly flexible data analysis platforms, factory floor systems and professional services.
HPL solutions have enabled companies to significantly improve yield by accelerating the process by which they identify, characterize and eliminate sources of failure throughout the entire product lifecycle. This is why a majority of the world's top twenty-five semiconductor and flat-panel manufacturers use HPL yield optimization solutions. www.hpl.com
Note:
HPL is a registered trademark of HPL Technologies, Inc. TechXpress, TDSRAM, and TestChip Advantage are trademarks of HPL Technologies, Inc.
All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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