32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Rhines draws roadmap for verification
EE Times: Latest News Rhines draws roadmap for verification | |
Ron Wilson (02/15/2005 8:35 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=60401191 | |
SAN JOSE, Calif. — Mentor Graphics Chairman and CEO Walden Rhines provided the DVCon conference here Tuesday (Feb. 15) with roadmap for achieving progress in the battle for design verification productivity. Rhines described the need for better verification. "Two- thirds of chip designs require at least two spins," Rhines said. "Three quarters of those cases are at least in part due to logic errors or other functional bugs — 80 percent of the time involving a design error." So what are design teams doing about it? Just working harder with the existing, increasingly incapable verification methodology, Rhines said. He noted that in another recent study only about a quarter of engineers said their job was verification; those who instead said their job was design reported spending half their time on verification tasks. "Complexity is breaking the methodology," Rhines said. "In response, verification tools are changing quickly today. But engineers don't like to change. Most engineers — although there are a few advanced teams — most engineers will keep using the same methodology until it completely fails, not matter how slow or hard it gets." Rhines described a two-phase shift away from the existing verification style. First, he predicted, teams would find that old techniques simply fail to cope with the complexity of their next design. "Then the tipping point," he said, "will come with the availability of new standards — System Verilog, VHDL, SystemC and PSL — that will reduce risk of adoption, improve reuse and create some real market competition for a new way of conducting verification." Alternatives are available today. There are three major changes in verification methodology: the use of assertions, reliance on accurate coverage metrics and a higher level of abstraction. "Experts tell me that you should have an assertion in your code just about everywhere that you would put a comment: An assertion every ten lines is not unrealistic," Rhines said. "This represents a big increase in front-end work, but it pays off." But it only pays off, he continued, with accurate coverage metrics. Rhines dismissed code coverage as not even measuring functional coverage in a real design. He said that coverage was a two-dimensional problem. Rhines said increasing the level of abstraction in verification was just as important as it was in design. "At the algorithm level we have to move from looking at events to looking at transactions," he said. Similarly, at the code level, there needs to be a shift from examining RTL to working with synthesizable C-code or with preverified modules. At the methodology level, there is a need to move from nuts and bolts verification tools to what Rhines called verification appliances, and to verification kits and verification IP libraries. In the future, Rhines said, verification engines will emerge that combine simulation and formal analysis. Tools will also emerge that can examine a design and automatically sequence the verification algorithms that will be applied to it. These tools will be directed to completion by meaningful design metrics. These measures, Rhines maintained, would launch a new and productive era for design verification.
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |
Related News
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- New Wave Design and Verification Announces Strategic Brand Evolution to Sharpen Focus on Innovation and Growth
- New Wave Design and Verification Appoints Darlene Weiss as Director of Human Resources
- INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with Siemens' advanced analog and mixed-signal EDA technology
- AMIQ EDA Releases Major Customer-Focused Product Line Update
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |