Chartered Provides Early Access to Design-Ready 65-Nanometer Process Platform for 300mm Manufacturing

Leading foundry ready for designers at 65nm; provides customers early access to process specifications and guidelines needed to design advanced SoC products

MILPITAS, Calif. and SINGAPORE - February 28, 2005 - Chartered Semiconductor Manufacturing (Nasdaq: CHRT and SGX-ST: Chartered), one of the world's top dedicated semiconductor foundries, today announced the initial deliverables for the 65-nanometer (nm) process platform - jointly developed with IBM, Infineon and Samsung - to support market leaders designing their next-generation products.

Available immediately, Chartered offers customers a comprehensive 65nm design manual and SPICE models, for equipping design engineers with the requisite process/design deliverables for designing complex system-on-chip products. These process/design technical parameters and specifications are available for both the base and low-power processes. To facilitate design validation by customers and design solutions partners, Chartered is planning to offer 65nm multi-project wafers at its 300-millimeter (mm) Fab 7 in the fourth quarter of 2005. Pilot production at 300mm on 65nm base and low-power processes is scheduled to take place in early 2006.

"At 65nm, we are executing to a leadership strategy with our development partners and Chartered's manufacturing team that places us in a position for engaging customers whose product strategies and capabilities are designed for fueling innovation in the market place," said Dr. Shi-Chung "SC" Sun, senior vice president of technology development at Chartered. "Our initial 65nm devices have demonstrated an excellent balance between performance and power consumption. It has been a true team effort among our partners to make this achievement possible."

The 65nm process platform, which targets logic, mixed-signal and multiple input/output voltage applications, offers a triple-gate oxide option with up to nine layers of copper interconnect plus redistribution layer, and low-k inter-metal dielectrics. Compared to the 90nm node, the 65nm process provides a 28 percent linear shrink in layout rules and a 50 percent reduction in overall chip area, with gate densities expected to improve by 200 percent. Platform offerings include base, low-power and high-performance transistors with multiple threshold voltages. Regular and dense SRAM bit cells are also available for the 65nm base and low-power processes.

As detailed by a joint-development team in its paper at the 2004 International Electron Devices Meeting (IEDM), low-leakage ultra-thin gate oxide and enhanced technology features are enabling significant transistor performance improvement in drive and off state currents, compared with 90nm technologies.

About Chartered

Chartered Semiconductor Manufacturing (Nasdaq: CHRT, SGX-ST: CHARTERED), one of the world's top dedicated semiconductor foundries, offers leading-edge technologies down to 90 nanometer (nm), enabling today's system-on-chip designs. The company further serves the needs of customers through its collaborative, joint development approach on a technology roadmap that extends to 45nm. Chartered's strategy is based on open and comprehensive design enablement solutions, manufacturing enhancement methodologies, and a commitment to flexible sourcing. In Singapore, the company operates a 300mm fabrication facility and four 200mm facilities. Information about Chartered can be found at http://www.charteredsemi.com.

Chartered Safe Harbor Statement under the provisions of the United States Private Securities Litigation Reform Act of 1995

This news release contains forward-looking statements, as defined in the safe harbor provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements, including without limitation, the statements relating to availability of 65nm multi-project wafers at Fab 7, commencement of pilot production of 65nm base and low-power processes in early 2006 and the expected improvement of gate densities are subject to certain risks and uncertainties, which could cause actual results to differ materially. Among the factors that could cause actual results to differ materially are the successful implementation of our joint development agreement with IBM, Infineon and Samsung, the continued success in our technological advances; customer demands; unforeseen delays or interruptions in our plans for our fabrication facilities; our progress on leading edge products; the rate of semiconductor market recovery, market outlook and trends; economic conditions in the United States as well as globally and competition. Although we believe the expectations reflected in such forward-looking statements are based upon reasonable assumptions, we can give no assurance that our expectations will be attained. In addition to the foregoing factors, a description of certain other risks and uncertainties which could cause actual results to differ materially can be found in the section captioned "Risk Factors" in our Annual Report on Form 20-F filed with the U.S. Securities and Exchange Commission. You are cautioned not to place undue reliance on these forward-looking statements, which are based on the current view of management on future events. We undertake no obligation to publicly update or revise any forward-looking statements, whether as a result of new information, future events or otherwise.