World's first ITU-T G.729A compliant Voice Codec Hardware Accelerator by Noesis Technologies

November 27, 2012 – Noesis Technologies announced today the immediate availability of its ITU-T G729A compliant voice codec IP Core. The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandwidth efficient, high speed quality voice coding algorithms. The ITU-T G.729A CS-ACELP is a high speech quality, low-bit rate (8kbps) codec that has been proposed to meet the voice compression requirements of a modern communication system. However the real time SW implementation of a multi-channel ITU-T G.729A compliant voice codec in conventional DSP processors is prohibitive due to the intensive amount of signal processing power required by the algorithm. To overcome this limitation Noesis Technologies has developed a revolutionized, highly efficient hybrid architecture that implements real time multi-channel G729A voice coding and exhibits the best performance-silicon area ratio available in the industry. The ntG729 IP Core can be used as a coprocessor to any processor type and can save significant computing resources for the main processor by efficiently executing the computationally intensive speech coding G729A algorithmic operations.

Performance Metrics

The ntG729 hardware accelerator when compared with a software implementation of ITU-T G729A algorithm on high-end processors, presents impressive competitive advantages:

• Outperforms by a factor of two by supporting twice as many voice channels.
• It requires only half the gate count thus increasing power efficiency and reducing costs.
• It presents an overall performance/silicon area ratio four times better than any high-end processor of the market.

Applications

Noesis Technologies ntG729 IP Core can be integrated in a variety of end-products including access devices, audio/video conferencing equipment, call center equipment, IP phones, IP/PBXs, VoIP gateways, System on Chip (SoC) VoIP processors. The core can be delivered as RTL source code, FPGA or ASIC (GDSII) netlist, under an End-User License Agreement.

About Noesis Technologies L.P.

Noesis Technologies, L.P. is a silicon IP provider specialized in hardware implementation of high computational complexity telecom algorithms. Our hardware accelerator IP solutions allow telecom system developers to significantly off load demanding tasks from the CPU and to drastically decrease execution time thus boosting the overall system performance. Our IP cores present an industry leading combination of high performance, low power and low die-area, as well as easy customization for adaptability to a wide range of applications. Noesis offers a complete portfolio of Forward Error Correction IP core solutions that includes Reed Solomon Codecs, Viterbi Decoders, Turbo Product and Turbo Convolutional Codecs, BCH codecs, (De)Interleavers, Channel Emulators. The company additionally offers a range of cores in the areas of security, networking, audio/voice compression and telecom DSP. Our solutions have been integrated in our customers’ end-products in telecom, aerospace and defense systems. Noesis Technologies is headquartered at Patras Science Park, GR 26504 Patras, Greece and has offices at San Jose, CA 95134, USA.

For more information please visit www.noesis-tech.com