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Arasan announced the availability of the MIPI® D-PHY IP compliant with the v1.0 standard released September 22, 2009 by the MIPI Alliance. With this release, Arasan continues to demonstrate its commitment to its Strategic Mobile Initiative by being the first to deliver fully verified MIPI IP comprising of software stacks, controllers and the D-PHY.
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Virage today announced new additions to its recently introduced SiPro(TM) product line of production-proven advanced interface IP. The expanded product line now includes complete standards-based solutions for PCI Express (PCIe) and Mobile Industry Processor Interface (MIPI(R)) as well as a unique multi-protocol IP solution for High-Definition Multimedia Interface (HDMI), Digital Visual Interface (DVI) and DisplayPort interfaces. The Virage Logic SiPro product portfolio is the result of a collaboration with AMD (NYSE: AMD) that was announced in January 2009.
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Intel Corp. will claim 94 percent of the netbook/smartbook market in 2009 but ARM Holdings plc and its processor licensees with take the lead in 2012, according to Robert Castellano of market research company The Information Network (New Tripoli, Pennsylvania).
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AMCC and TSMC today announced a collaboration enabling AppliedMicro’s Power Architecture® microprocessors to be manufactured on TSMC’s industry-leading technology platform first at 90nm then moving to 65nm and 40nm soon after.
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Sidense today announced that Faraday selected Sidense’s 1T-Fuse™ single- transistor bit cell, one-time programmable (OTP) macros for use in a USB secure drive application. The 16Kbit Sidense macro provides a highly secure storage medium for protecting data, applications and IDs on the drive.
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ARM has introduced multi-drop support into the ARM® CoreSight™ Serial Wire Debug (SWD) solution, enabling simultaneous connection to multiple devices from a single debug host.This latest version of SWD with multi-drop support brings a high performance and low cost 2-pin debug solution to complex, multi-core, multi-chip products such as mobile devices, making debug implementation more affordable in the end product.
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Synopsys today announced the company will be the first IP vendor to show SuperSpeed USB 3.0 data transfers of an xHCI Host, Hub and Device digital controller IP in a single demonstration.
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ARM has developed mbed, the industry's first online platform for fast, low-risk prototyping of microcontroller-based systems. The mbed tools launch with integral hardware and software support for the NXP LPC1768 ARM® Cortex™-M3 processor-based MCU, making cutting-edge microcontroller technology accessible to a wide audience.
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IBM has successfully developed a prototype of the semiconductor industry's smallest, densest and fastest on-chip dynamic memory device in next-generation, 32-nanometer, silicon-on-insulator (SOI) technology that can offer improved speed, power savings and reliability for products ranging from servers to consumer electronics.
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Faraday Technology today announced that their SATA 3G solution is the first to pass SATA-IO compliance test in UMC's 90 nanometer process technology, and becomes the 2nd IP provider in the world to have IP in SATA-IO's Building Block Listing.
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ARM announced today the development of two Cortex™-A9 MPCore™ hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.
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IBM Corporation today announced the industry's highest performance, highest throughput processor for system-on-chip (SoC) product families in the communication, storage, consumer, and aerospace and defense markets
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New Scalable Platform Combines Programmable Precision Analog and Digital Logic with High Performance ARM-Cortex M3 and 8051-Based MCU Sub-Systems, Delivering Unmatched Time-to-Market, Integration, and Flexibility for 8-, 16- and 32-bit Applications
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PRISTINE is a PCIe x8 board designed to handle uncompressed audiovisual material for its compression & decompression with JPEG 2000, faster than real-time. PRISTINE also provides a 3GSDI interface with four 3G inputs and outputs. PRISTINE supports virtually all SD, HD, 2K and 4K formats and offers embedded audio channels.
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ARM and Cypress announced today that Cypress has licensed a broad range of intellectual property (IP) from ARM for use in next-generation programmable platforms. Cypress has licensed the ARM® Cortex™-M3 and ARM9™ family processors, along with more than 75 other IP elements.
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Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard.
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The ECONA CNS3XXX Family of Single and Dual Core ARM® SoC Processors Enable High Performance, Intelligent Home Networks While Slashing Power and Cost for Next-Generation Gateways, Storage and Consumer Electronics (CE) Devices in the Digital Home
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Advanced Technology Investment Company LLC (ATIC) of Abu Dhabi and Chartered Semiconductor Manufacturing (Chartered) of Singapore today announced a definitive agreement whereby ATIC would acquire Chartered, one of the world’s top dedicated semiconductor foundries.
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What do July's chip figures mean? So far, analysts from Carnegie ASA, Gartner and Semico have separately interpreted the data. Now, Cowan, Databeans and Semiconductor Intelligence have added fuel to the fire.
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Mentor Graphics today announced Precise-IP™ — a new vendor-independent IP (Intellectual Property) platform as part of the Mentor Graphics® Precision® Synthesis product line. The platform includes vendor-independent configurable IP from Mentor Graphics and links to categorized third-party IP from leading vendors.
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Freescale Semiconductor Inc. plans to transfer its 3G cellular intellectual property (IP) to Beijing Capital Semiconductor in a deal valued at between $30 million and $40 million, according to a market analyst.
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EVE today announced that its new emulation system ZeBu-Server supports high-capacity designs of up to one-billion application specific integrated circuit (ASIC) gates.
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