The wide range PLL is an ultra low-power, low jitter design which operates with single 1.2V supply. This PLL satisfies clock needs for a wide range of data communication applications.
The architecture is based on self biased technique which technically overcomes the design trade-offs existing between wide frequency range and low jitter. It virtually removes all process, technology and environmental variability in PLL designs. This IP avoids the use of external biasing circuit and filters.
- Single 1.2V Supply
- VCO range from 700MHz to 2.0GHz.
- Input frequency range of 17MHz to 50MHz
- Ultra Low power consumption
- Low Jitter
- Lock time less than 20uS.
- Programmable Dividers.
- Power down mode
- Fujitsu 65nm 7 metal
- Suitable for very low power applications
- Wide functional range
- Avoids external biasing and filtering circuits
- LVS netlist
- Behavioural Model
- IP Integration support