LVDS18 RX belong to Sankalps 28nm IO library. Power supply sequencing independent (PSSI), 9-layer metallization with north - south and east-west variants and flipchip packages are the salient features for this cell. The foot print of LVDS18 rx noterm ns, LVDS18 rx noterm ew, LVDS18 rx term ns and LVDS18 rx term ew is 70μm x 175μm. Sankalp's LVDS is silicon proven in TSMC 28 nm HPM process.
- Supports 702 metal stacks with north-south and east-west variants.
- Supports PCI Express Gen-3 Reference clock receiver specification.
- Operates in junction temperature ranges from -40 to 125 degrees Celsius.
- Powered from 1.8V ± 10% IO supply and 0.9V ± 7% or 1.0V ±5% Core supply.
- Operates up to 2Vpp input differential voltage
- Input voltage range from 0V to 2.4V
- No Power supply sequence restrictions.
- ESD hardness of 2KV HBM, 500V CDM and +/-100mA current injection for latch up.
- Sankalp’s process optimized General Purpose cell set is very comprehensive and it would meet the critical performance, power, area, and reliability requirements for today’s system-on-chip design
- Low power
- Smaller Foot Print
- Higher Pad to PG ratio
- Faster Integration
- Services Available with this Product
- SOC Integration
- Application & ESD Guidance
- Signal Integrity Analysis & Guidelines
- Characterization Support
- LVS netlist
- Verilog Model
- Timing Model