The 10/100/1000 Base-T Gigabit Phy designed in TSMC 65nm to support 10G Base KR4 standard.
- Supports channel at 5.275Ghz/10.55Gbps and BER <10-17
- Built in self test (BIST) through SLB from Trans-mitter and Receiver ports.
- Full duplex core in 2/4 ports are available
- Tunable Transmitter output amplitude with 3 Lap FIR
- Tunable Automatic Gain Control with 5 Lap DFE
- Power Supply: 1.2V/ 1.8V (nominal),
- Temp: -40 and 125 0C
- Asynchronous clock and data recovery
- Complaint with 802.ap
- Compatible with IEEE 1149.6-2003 AC JTAG
- 50 ohm on-chip termination at transmitter and receiver with ± 3% variation
- HBM complaint ESD protection
- Single Supply:1.2V±0.1v, Multi Satndard with Programmable Pre-Emphasis and equalizer supporting 10G Base KR4 standard.
- GDSII layout and Map-ping files
- LVS compatible netlist
- Verilog-A Model