The nSAD10100_UM18m_1A is a high-speed and low power 10 bits analog-to-digital converter. It achieves 61dBc SFDR conversion linearity, silicon proven. It is built around a fully differential proprietary time enhanced pipeline converter and a digital error correction circuitry.
This ADC IP includes an internal reference voltage generator and an internal bias circuitry. Optionally, a dedicated input buffer can be added for an easier interface to your analog/RF front-end.
- UMC 180nm 1.8V CMOS process with MIM capacitors (optional)
- Single 1.8V supply
- up to 100 Mspls/s sampling rate
- 2Vpp_diff input dynamic range
- DNL = ±0.5 LSB typ., INL = ±0.7 LSB
- Fully internal reference voltage generator and bias circuitry
- Proprietary conversion scheduling for lower power consumption
- only 66mW typical at 100Mspls/s
- 1.1 mm2 core area including reference generator, biasing and internal decoupling
- Power down mode
- SNR and SFDR figures
Block Diagram of the 10-Bit 100MS/s 1.8V 66mW ADC, CMOS 180nm