The 10-bit dual ADC IP operates up to 125MS/s and dissipates only 87mW over a single 1.2V supply including auxiliary circuits. For maximum flexibility, the power dissipation of the ADC scales with the sampling frequency.
The ADC employs a high-performance front-end input sample-and-hold circuit together with a differential pipeline architecture and digital error correction. The ADC input can be fully-differential or single-ended.
The S/H features an analog input bandwidth of up to 750MHz and can operate in under-sampling mode for communications applications.
This 10-bit dual ADC features an excellent static performance that includes ±0.5LSB DNL and ±1.5LSB INL.
Channel-to-channel matching includes I/Q gain and phase matching better than, respectively, 0.2dB and 0.5º. Dynamic performance highlights considering an input signal with 10MHz frequency and 125MS/s sampling rate include an SNR of 52.5dB, SFDR of 63dB and 8.3-bit ENOB.
Auxiliary circuits comprising a bandgap circuit, frequencydependent current biasing and voltage reference buffers with internal decoupling are also included to provide a complete ADC solution.
The 10-Bit 125MS/s IQ ADC can be cost-effectively ported across foundries and process nodes upon request.
- 65nm SMIC LL, 6 Metals Used
- No Analog Options
- Single 1.2V Supply
- Dual Pipeline ADC
- Sampling Rate of 125MS/s
- 1.0Vpp Diff. or 1.0Vpp Single-Ended Input Range
- S/H with 750MHz Full Power Bandwidth
- DNL= ±0.5LSB Typ.; INL= ±1.5LSB Typ.
- SNR= 52.5dB at fin= 10MHz and 125MS/s
- SFDR= 63dB at fin= 10MHz and 125MS/s
- 8.3-bit ENOB at fin= 10MHz and 125MS/s
- Stand-By and Power-Down Modes
- Low Power
- Compact Die Area
Block Diagram of the 10-Bit 125MS/s IQ ADC - SMIC 65nm LL