The Xelic 100Gb/s Frame Mapped GFP OTN Mapper Core (XCG4M) contains a Frame Mapped GFP processor and an integrated ODUk mapper supporting ODUFLEX and fixed rate frames up to 100Gb/s (ODU4). XCG4M Transmit and Receive Processors provide the mapping and demapping of variable rate Ethernet client data streams into ODUk frames with Client Signal Fail capability and programmable consequential actions for flexible configurations. Client data is transferred using a 512-bit data bus operating up to 210MHz and line side data is transferred through a data request/valid scheme using a 640-bit data bus operating at a clock rate up to 180MHz.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.7041/Y1303 and ITU-T G.709 specifications.
- GFP-F Processing
- Provides test mode for generation of user specified client data or client management frame types.
- Optionally calculates and inserts FCS field information.
- Supports GFP frame mapped mode of operation.
- Provides 16-bit counters for the accumulation of GFP control frames generated, client data packets transmitted, and client management packets transmitted.
- Supports pad character insertion for SOP error conditions.
- Supports control frame (idle) insertion for GFP frame rate adaptation
- Optional GFP frame payload type field configuration through external pins or internal register programming
- Detects SOP/EOP errors, invalid client data transfers and provides optional FIFO flush capability for SOP errors.
- Provides test features which includes the ability to force GFP control frames and corrupt cHEC and/or tHEC fields for a programmable number of frames.
- Performs frame delineation on incoming GFP frames with optional cHEC scrambling.
- Provides programmable delineator in-frame count capability.
- Supports frame mapped mode of operation.
- Supports core header single bit error correction (optional) and multiple bit error detection.
- Supports type payload header single bit error correction (optional) and multiple bit error detection.
- Provides detection and accumulation of SSF errors, FCS errors, core header corrected, payload header corrected, payload headed uncorrected, control frame, client management packet, client data packet, and client invalid packet conditions to provide an indication of health status for the incoming GFP data link.
- Detects and reports invalid extension header and/or payload type identifiers.
- Provides maskable interrupts for user selectable detection reporting.
- OTN Mapper/Demapper
- Maps GFP-F data into generated ODUk frames.
- Inserts framing and OPUk overhead.
- Supports data request scheme for overclocked applications.
- Demaps GFP-F data from incoming ODUk frames.
- Performs frame alignment check and provides signal fail detection and generation.
- Supports data valid scheme for overclocked applications.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).