The 100G Ethernet Media Access Controller (MAC) implements essential protocol requirements for operation of 100 Gbp/s Ethernet (IEEE 802.3ba) compliant node. The 100GMAC IP Core supports configurable FIFO's on both transmit and receive side to handle application's latency during the frame transmission and reception. The 100GMAC is compliant to IEEE 802.x standard for full-duplex operations by supporting PAUSE frame and PAUSE operations. The 100G MAC is architected for both ASIC and FPGA implementations using a standard tool flow.
- 100Gbps IEEE 802.3ba Compliant MAC
- Support for IEEE 802.3 (2008)
- Small footprint design for low area and
- power savings
- Optimized for ASIC implementations
- Configurable Data path (128/256/320 bits)
- IEEE-802.3ba compliant CGMII like interface (Clause 81) with 128 bit data, 16 bit control or 256 bit data, 32 bit control or
- 320-bit data, 40-bit control to interface to 100G PCS Module.
- Interfaces with application side with a Flexible FIFO interface with control for easy integration
- PAUSE Flow Control and Priority Pause Frames
- 64-bit Counters for Statistics
- Up to 3 VLAN Q-Tag Frame support. Accounts for the VLAN tags whilechecking for the Max Frame Length.
- Full-Duplex mode of operation while supporting PAUSE frame based flow control.
- 802.3 Compliant MIB, SNMP, RMON management support by using variety of 64-bit counters.
- Configurable Transmit and Receive FIFO's.
- Supports Jumbo Frames during both transmit and receive operations.
- Provides a simple Registers Interface to read/write registers for control and configuration of the 100GMAC.
- FPGA support available
Block Diagram of the 100G Ethernet MAC (Media Access Controller) IP Core