The IEEE802.1AE AES-256 GCM MAC-SEC (MACsec) Encryption IP Core provides full line rate classification, encryption/decryption, authentication, anti-replay services for 100GbE (100Gb/s) operation. Supports reduced size build to support 40GbE operation as well.
Compliant to XPN-MAC-SEC draft update to IEEE802.1AE specification to support 64-bit Packet Sequence Numbers.
- Soft RTL to target either FPGA family or portable to ASIC libraries. Also has optimized build for targeting Xilinx Virtex-6/7 FPGAs with reduced resources.
- Highly Configurable IP to trade off resources used (Block RAM vs Logic), FIFO Depth, number of Security Associations supported.
- Includes AXI4 Lite Control & Status interfaces for each block of design and a C++ API to setup the IP Core for MACsec Encryption.
- 100GbE Line Rate Encryption, Decryption, Authentication, and Anti-Replay services.
- Full Source Code (VHDL).
- SystemC/VHDL Module & System Level Test Benches. Verification Environment runs discrete test sequences and constrained Random coverage.
- SystemC TLM2.0 Model available.
- C++ MACsec Reference Model.
- C++ API for control/status of IP Core.
- 100Gb/s Reference Design (Complete System) available.
- Synthesis, Place & Route scripts for parallel Xilinx compile.
Block Diagram of the 100Gb/s AES GCM MAC-SEC Encryption IP Core