The Xelic 10Gb/s I.7 Enhanced Forward Error Correction (EFEC) Core (XCO2EFEC7) generates codeword parity bits and performs error detection and correction for OTN OTU2 frames. The XCO2EFEC7 contains independent encoder and decoder functions with two orthogonally concatenated BCH codes, providing 7 overhead. The XCO2EFEC7 is compliant with the G975.1.I.7 specification and has been through extensive interoperability testing. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU2 rate using a 64-bit data bus operating at 167.33MHz.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO2EFEC7 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.7 specification.
- Contains 7 parity overhead.
- Encoder includes single bit error insertion for diagnostic purposes.
- Decoder includes five iterative stages of BCH error correction, Row1 Col1 Row2 Col2 Row3.
- Each decode stage can be disabled via input control signals.
- Provides corrected ones and corrected zeroes outputs.
- Provides uncorrected codeword outputs.
- Provides status outputs for internal MSYNC state machine.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Overall latency of 140us.