The Xelic 10Gb Media Independent Interface (XGMII) to 10GBASE-R PCS Core (XCI2PX) performs mapping of XGMII signals into 66-bit PCS blocks (and vice-versa) using a 64B/66B coding scheme. 10GBASE-R and 10GBASE-W applications are supported with 64B/66B transmission codes transferred at a 10Gb/s rate using a 64- bit data bus operating at 161.13Mb/s.
The XCI2PX Encode Processor accepts incoming XGMII based formatted data, encodes the data and continuously generates PCS blocks. Ordered sets and idle blocks can optionally be inserted. Programmable bypass and loopback modes of operation are supported. In addition, test block insertion is provided for diagnostic purposes. Optional scrambling is also available on the outgoing PCS based data.
The XCI2PX Decode Processor contains a configurable block synchronizer with options for block descrambling capability. A BER monitor provides an indication of signal integrity for incoming data blocks. XGMII based ordered sets are optionally inserted for programmable LOS and high BER error detection. When appropriate status has been achieved, the decode processor continuously accepts PCS blocks and generates XGMII based codes.
Performance counters are provided for the accumulation of Synchronization Block Error and high BER Error conditions in the XCI2PX decode processor. In addition, the encode processor contains Ordered Set and Test Block Mismatch performance counters. All counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCI2PX provides facility and terminal loopback modes of operation using Decode and Encode Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCI2PX core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Provides for bypass and normal modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Supports decode and encode facility and terminal loopback configurations.
- Performs PCS code generation from incoming XGMII based codes
- Provides optional scrambling (1 + x39 + x58) with polynomial corruption capability for diagnostics.
- Supports programmable Ordered Set Block and Idle block insertion.
- Supports programmable test block detection with interrupt reporting capability.
- Performance Ordered Set and Test Block Mismatch counters are provided.
- Performs XGMII code generation from incoming PCS blocks.
- Provides block synchronization with programmable Out Of Block Lock (OOBL) and Loss Of Block Lock (LOBL) detection and maskable interrupt capability.
- Supports incoming BER monitoring with optional interrupt reporting.
- Supports programmable Test Block insertion for diagnostic purposes.
- Provides optional descrambling (1 + x39 + x58) with polynomial corruption capability for diagnostics.
- Inserts programmable Ordered Set blocks for a variety of maskable error conditions including receive LOS and high BER detection.
- Performance Synchronization Block Error, high BER Error and Block Idle counters are provided with user defined interval or errored second accumulation.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).