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11 Bit 120 MSPS Multi-Mode Sigma Delta Dual ADC

This dual channel ADC accepts an input clock of up to 120Mhz, depending on required bandwidth. It uses the 2 ADC cores with shared references and timing, to ensure excellent phase and gain matching performance.

The ADC has differential inputs in order to maximize dynamic range and noise immunity. The ADC is preceded by a bypassable integrated buffer which allows the ADC to accept an input signal amplitude of 1Vpk-pk.The exclusion of this buffer limits the ADC to an input range of 0.5Vpk-pk but offers better power performance.

The ADCï¿½s power is scalable with sample frequency.

Features

Dual IQ ADCs and bandgap
Power/sample rate scalability

37mW @ 120 MSPS
23mW @ 75 MSPS
15mW @ 30 MSPS

9mW @ 3.75 MSPS

Dynamic Performance

67dB SNDR
78dB SFDR

90nm 6 Metal CMOS process (No analog options)
1.2V power supply
Die area of 0.65mm2 (inclusive of decimation filter and bandgap)

Deliverables

As part of the License Agreement the components listed will be delivered:

Datasheet
Characterization Report
Flat Netlist (cdl)
Layout View (gds2)
Abstract View (lef)
Timing View (lib)
Behavioral Model (VHDL/Verilog)
Silicon Samples
DemonstrationEvaluation Board

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11 Bit 120 MSPS Multi-Mode Sigma Delta Dual ADC

Features

Deliverables

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11 Bit Sigma Delta Dual ADC

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