The 14-Bit 15MS/s Dual ADC is a low-power dual-channel ADC IP operating up to 15MS/s and dissipating 50mW at 15MS/s, including auxiliary circuits.
The ADC employs a differential pipeline architecture and digital error correction.
This ADC IP features an excellent static performance that includes ±0.8LSB DNL and ±4.0LSB INL at 14-bit resolution.
Dynamic performance highlights, considering an input signal with 0.8MHz frequency and 15MS/s sampling rate, include an SNR of 70.5dB, SFDR of 78dBc and 11-bit ENOB measured over Nyquist.
Auxiliary circuits comprising a bandgap circuit, operating mode controls and voltage reference buffers with external decoupling are also included to provide a complete ADC solution.
The 14-Bit 15MS/s Dual ADC can be cost-effectively ported across foundries and process nodes upon request.
- TSMC 0.18um Generic CMOS High Voltage Mixed- Signal
- Single 1.8V Power Supply
- 16MS/s Maximum Sampling Rate
- 2.0Vpp Differential Input Range
- Low Power Dissipation
- DNL= ±0.8LSB Typ.; INL= ±4.0LSB Typ.
- SNR= 70.5dB at fin= 0.8MHz and 15MS/s
- SFDR= 78dBc at fin= 0.8MHz and 15MS/s
- 11-bit ENOB at fin= 0.8MHz and 15MS/s
- Stand-By and Power-Down Modes
- Small Die Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
- Video Applications
- Wireless Communications
- General Purpose Data Acquisition
Block Diagram of the 14-Bit 15MS/s Dual ADC IP Core