This macro from Cadence Design Systems is a 14-bit 308 MHz analog to digital converter (ADC) designed using the TSMC 65nm G process.
This ADC incorporates a successive approximation register (SAR) type architecture. The ADC will incorporate 8 parallel SAR ADCs. Each SAR ADC requires 16 internal 616MHz clock cycles to complete a full 14-Bit conversion.
Reference voltages and bias currents are derived from an internal bandgap voltage and an external resistor. In power down mode these are turned off and the power supply current is reduced to keep alive levels.
- 14-bit Analog to Digital Converter
- 300MHz maximum sample rate
- High impedance Input Buffer
- Ultra high bandwidth low jitter sampler for above Nyquist sampling
- High SFDR, >75 dB with 200 MHz input
- Parallel Successive Approximation Register Architecture
- Minimal off chip components required
- Power down mode
- Analog test bus for pre production testing
- Uses metals M1 – M8 + RDL: (M1+5X+1Z+1U+RDL)
- Suitable in the following applications:
- Wireless Applications
- High Speed Analog to Digital Conversions
- SoC systems
- Standard Integration Views
- Integration Support