The APS DSP co-processor core is a fixed point general purpose 16 bit DSP extension to the APS family of processors. It extends both the instruction set and register set of the main CPU enhancing the performance of the system for numerous applications. It provides two additional memory interfaces, ensuring the memory bandwidth necessary for demanding signal processing applications.
It has three ALUs operating in parallel, allowing one arithmetic operation and two address calculations per cycle.
The address ALUs support a number of addressing modes, implementing circular buffers and bit reverse arithmetic without additional program support. Two 32k by 32 bit memory interfaces give algorithms ample and efficient access to parameters.
The main ALU has four 16 bit general purpose registers and two 20 bit accumulators. A 16 ´ 16 multiplier gives 20 bit results. The address ALUs have four address pointers each associated with an offset register and circular buffer register, all of which are 16 bits long.
The Zero Overhead Loop (zol) construct allows part of an algorithm to be iterated automatically. The instructions are stored in an internal buffer and are only required to be fetched once for the entire loop. This loop then executes completely in parallel to the application running on the main CPU.
The Harvard bus architecture ensures simple memory design. Dual memory interfaces ensure that each instruction can perform two memory accesses as well as the instruction fetch.