The 2Ror1W SRAM Algorithmic Memory generator is capable of generating a wide range of memory cores based on user defined parameters. The 2Ror1W memory is capable of Reading on the first port and Writing on the second port. All transactions are synchronous to a single clock and can occur simultaneously.
- Up to 40% Area and Power Savings
- Up to 30% Performance Improvement
- Supports a wide range of memory instances up to 16Mbit
- Allows simultaneous random accesses, even to same row, column.
- No additional clock latency over physical memory macros.
- Exhaustively verified using adversarial models and formal methods
- Uses a standard SRAM interface with identical pinout to standard physical memory
- Seamless integration into existing ASIC design flows
- Transparent to customer BIST/BISR and industry standard DFT methodologies
- The output of the Renaissance 2X Memory Generator is a comprehensive set of fully verified model that can be supported by major EDA tools:
- Synthesizable RTL core (encrypted)
- Sample Synthesis Scripts & Timing Constraints
- Functional Test Vectors & Testbench environment
- Generic Datasheet, Instance Datasheet
- Integration Guide
- Release Notes & Readme
- User Guide