Implemented on TSMC 28HPC, the IP is a power optimized implementation of the CEI 28GSR standard, and has been designed to accommodate slightly higher frequencies (to 32G).
Our proprietary digital architecture drives on significant digital gates to calibrate, nullify, and cancel and non-idealities inherent to very deep sub-micron CMOS.
The design includes industry-leading DFT and comes with the platinum onsite bring-up support package - OmniPhy design engineers sitting on the customer site to bring up the design and launch it into production.
- Compliant to CEI28SR standard, capable up to 32G
- Special modes for ultra-low power dissipation, and very short reach links
- Over 10 digital calibration loops work simultaneously to reduce and cancel the effects of deterministic jitter
- Post-silicon trim features
- On-board self-diagnostics
- Ready for customer integration today
- Lowest power solution on the market
- Best and most robust DFT on the market
- Robust ESD with on-die capacitive cancellation
- On-site support
- PCS RTL: soft-IP with design constraints for physical implementation
- SerDes PMA behavioral model along with test benches for verification
- LEF abstracts for physical implementation
- Liberty Timing Views (.lib) for multi-corner timing analysis
- GDSII with DFM for high manufacturability
- DFT Models: Scan models for the hard-macro for ATE vector generation
- Documentation: Data Sheets, PCS MAS, RTL Application Notes, SerDes Layout Integration Guidelines, Package/Board guidelines, Test Plan, DFT Specifications