This IP module is physical media attachment (PMA) for high speed interface between silicon chip link. It supports from 10Gbps to 28Gbps. The design support 20nm CMOS digital process. It can be configured to one lane or four lanes.
- Supported link protocol
- EPON(1.25G, 2.5G, 10G)
- Fibre Channel(1~12.75G)
- CE-11G SR/MR/LR (9.95 – 11.1Gbps)
- SFI5.2 (9.95 – 11.1 Gbps)
- SFI-S (9.95 – 11.1 Gbps)
- Low power design
- Configurable for low power application.
- Small footprint
- Low jitter PLL and CDR with SSC.
- No off-chip component are required.
- Adaptive receiver, and transmitter with FIR equalizer.
- Testability: AC JTAG,Boundary scan,SCAN,Multiple serial and parallel Loop backs,Pattern generator,Analog probe port.
- GDS2 with DFM for high yield purpose.
- LEF view.
- IP detail data sheet.
- Verilog RTL code for system level simulation.
- Liberty timing view for timing closure