Implements a 32-bit processor for demanding systems running applications on general-purpose operating systems such as Linux and Android. The high-performance BA25™ processor runs at high clock frequencies yet has a smaller silicon footprint than most competing application processors (e.g., over 800MHz and 350Kgates in TSMC65nmLP, 12-track library).
This royalty-free 32-bit processor core is binary-compatible with other members of the silicon-proven BA2x processor family. Its BA2 instruction set is relatively simple and extremely compact, offering system area and energy savings benefits. Programing is facilitated with the included C/C++ tool chain, Eclipse IDE, architectural simulator, and ported C libraries, RTOSs, and OSs
The seven-stage pipelined architecture runs at high frequencies and further enhances performance by supporting out-of-order execution and branch prediction. An optional IEEE 754 compliant floating-point unit accelerates floating point computation.
BA25 Block Diagram The BA25 processor uses two-level data and instruction caches—with L0 running at the CPU’s clock frequency and L1 running at half that—and a two-level memory management unit. The size and associativity of the caches and MMU are configurable at synthesis time. The system interface uses two AMBA® AXI4 buses, one for data and one for instructions, both of configurable data width. Two tightly-coupled quick memory (QMEM) buses allow fast access for time-critical code and data, and can be used for inter-core communication in a multi-core architecture.
The energy efficiency BA25 enables power management with clock gating and power shut-off of unused units, and through software and hardware control over the clock frequency of the CPU and buses. Wake-up from sleep mode is triggered by an interrupt issued by the embedded tick-timer or by an external source. Rapid interrupt response is facilitated by the embedded programmable vectored interrupt controller.
- High Performance 32-bit CPU
- Seven-Stage Pipeline
- Out-of Order Completion
- Sophisticated Branch Prediction
- Optional Floating Point Unit
- 1.7 DMIPS/MHz
- 2.0 Coremarks/MHz
- 800+ MHz on TSMC 65nm LP
- Efficient Power Management
- Dynamic clock gating and power shut-off of unused units
- Software- and hardware-controlled clock frequency
- Wake-up on tick timer or external interrupt
- Fast & Flexible Memory Access
- Separate Instruction and Data Caches and MMU
- AXI4 data & instruction buses (32-, 64- or 128-bit) with 4 GBytes direct addressable space on each bus
- Tightly coupled Quick Memory (QMEM) interface for fast and deterministic access to code and/or data
- Two-Level Cache and MMU
- L0 cache running at core frequency and L1 cache running at half the core frequency
- 1–16 Kbytes L0 caches, up to
- four-way set associative
- 32–512 Kbytes L1 caches, up to four-way set associative
- L0 MMU with up to 32 four-way associative entries
- L1 MMU with up to 2048 four-way associative entries
- Optional Integrated Peripherals
- Vectored Interrupt Controller
- Microcontroller peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
- Memory controllers, interconnect IP, and more
- Easy Software Development
- Non-intrusive JTAG debug/trace for both CPU and system
- Complex chained watchpoint and breakpoint conditions
- BeyondStudio™ complete IDE for Windows or Linux under Eclipse
- Ported libraries and operating systems
- The core is available for ASICs in synthesizable Verilog source code, and includes everything required for successful implementation. The core is delivered with software development tools Windows and Linux, with an Eclipse IDE interface.
Block Diagram of the 32-bit Advanced Application Processor