The IBM PowerPC 405 core is a 32-bit RISC CPU core providing up to 400 MHz and 608 DMIPS performance as implemented in IBM's advanced 90-nm copper CMOS technology. The 405 core employs the scalable and flexible Power Architecture technology, optimized for embedded applications.
The licensable embedded core integrates a scalar five-stage pipeline, separate instruction and data caches, a JTAG port, trace FIFO, multiple timers and a memory management unit (MMU), with 1.52 DMIPS/MHz performance.
The PowerPC 405 core's performance, low power specifications and design attributes make it an ideal solution for emerging consumer, storage and wired or wireless communications applications.
Features
- Compatible with the scalable and flexible PowerPC instruction set architecture to facilitate code reuse
- Optimized for high performance, low cost,and low power consumption system-on-a-chip (SOC) designs
- Supports product differentiation via inclusion of custom logic and/or low cost
- JTAG and Trace FIFO ports enable robust debug capabilities,even in complex SOC designs
- Available in the IBM Blue Logic core library for integration with peripheral and application-specific macro cores to develop SOC solutions Supported by over 75 third-party vendors in IBM 's PowerPC Embedded Tools TM Program
- Full-function simulation models are available to support SWIFT compliant VHDL and Verilog simulation environments
- PowerPC 405 CPU
- Compatible with PowerPC User Instruction Set Architecture
- Five-stage pipeline
- 32-bit x 32 general purpose registers
- Hardware multiply and divide
- Branch prediction
- Cache Controllers
- Separate I-and D-cache units
- Fill-first,data for arding
- Non-blocking flush operations
- Programmable loads and store
- Memory Management Unit
- Variable page sizes (1 KB-16 MB)
- 64-entry fully-associative TLB
- I/O Interfaces
- Processor Local Bus (PLB)
- Auxiliary Processing Unit (APU)
- On-Chip Memory (OCM)
- JTAG
- Timers
- 64-bit time-base
- Programmable interval timer
- Fi xed interval ti mer
- Watchdog timer
- Debug Support
- 4 Instruction Address,2 Data Address, and 2 Data Value breakpoints
- Real-time non-invasive trace
- Exclusive traceback capability
Benefits
- 405A3
- Technology : .25 um (.18 u m L eff ) CMOS SA-12E
- CPU Core Size (est.) : 2mm2
- Frequency (MHz): 0 to 200 WC1 , 0 to 300 TC1
- Performance (Dhrystone 2.1 MIPS) : 282 @200MHz , 423 @300MHz
- Power Dissipation (estimated,typical) : 1.0W @200MHz
- Voltage 2.5V +/-5%
- I-Cache : 32K
- D-Cache : 32K
- MMU : Yes
- Timers : Ye s
- JTAG : Ye s
- Trace FIFO : Yes
- 405B3
- Technology : .25 um (.18 um L eff ) CMOS SA-27E
- CPU Core Size (est.) : 1.4mm 2
- Frequency (MHz) : 0 to 200 WC2, 0 to 300 TC1
- Performance (Dhrystone 2.1 MIPS): 282 @200MHz ; 423 @300MHz
- Power Dissipation (estimated,typical): 650mW @200MHz
- Voltage : 2.5V +/-5%
- I-Cache : 16K
- D-Cache : 8K
- MMU : Yes
- Ti me r s : Ye s
- JTAG : Ye s
- Trace FIFO : Ye s
- 405D4
- Technology : .18 um (.11 um L eff ) CMOS SA-27E
- CPU Core Size (est.) : 1.4mm 2
- Frequency (MHz) : 0 to 266 WC2; 0 to 390 TC2
- Performance (Dhrystone 2.1 MIPS) : 375 @266MHz; 550 @390MHz
- Power Dissipation (estimated,typical): 500mW @266MHz
- Voltage : 1.8V +/-5%
- I-Cache : 16K
- D-Cache: 16K
- MMU : Yes
- Timers : Yes
- JTAG : Ye s
- Trace FIFO: Yes
- WC1 Worst case conditions (2.3V,85 °C,slo silicon)TC1 Typical conditions (2.5V,55 °C,nominal silicon)
- WC2 Worst case conditions (1.65V,85 ° C,slo silicon)TC2 Typical conditions (1.8V,55 °C,nominal silicon)
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