The 3GPP LTE MIMO Encoder LogiCORE™ IP provides a flexible and highly optimized implementation of the MIMO encoding functions for LTE eNodeB applications, as defined in the 3GPP-LTE specifications. It represents one LogiCORE IP component in the broader LTE Baseband Platform developed by Xilinx.
- Implements layer mapping and pre-coding as defined in the 3GPP TS 36.211 v.9.1 specification
- Supports both transmit diversity and space division multiplexing schemes
- Cyclic delay diversity option
- Maximum theoretical throughput supported for systems with up to 20 MHz bandwidth
- Parametrizable input/output data precision
- Optimized for high performance Virtex-6 FPGAs
- Bit accurate behavioral C model available to accelerate simulations