The SVR-CSCP4 is designed to interface smoothly with commonly used Application Processors. It supports a clock lane and a data lane when in CCP2 mode. In CSI2 mode it supports a clock lane and up to four data lanes.
- CSI2 Mode functionality highlights include:
- Configurable 1,2,3 or 4 data lanes;
- Up to 1Gbps per lane;
- Interface signals as defined in Appendix B of MIPI CSI2 specifications;
- All CSI functionality implemented in hardware, freeing the CPU to other tasks
- Support of all data formats.
- Extensive set of registers, accessible by AMBA APB bus
- Programmable timing parameters
- CCP2 Mode functionality highlight include:
- Class 0, 1 and 2;
- Up to 650Mbps;
- Supporting all data formats as defined in Chapter 5 of the CCP2 Specifications
- Receiver Behavior as recommended in Chapter 8 of the CCP2 Specifications.
- A configuration bit (CSI/~CCP) defines the mode of operation.