40G/4x10G G975.1 I.7 Enhanced FEC Core

Features

• Optimized for ASIC implementations.
• Integration support and maintenance available.
• XCO23EFEC7 core available under flexible single use licensing terms with netlist or source code deliverables.
• Complies with ITU-T G.975.1 Amendment I.7 specification.
• Standard 7 percent parity overhead.
• Encoder includes single bit error insertion for diagnostic purposes.
• Decoder includes five iterative stages of BCH error correction, Row1 – Col1 – Row2 – Col2 – Row3.
• Each decode stage can be disabled under via input control signals.
• Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
• Provides uncorrected codeword outputs.
• Provides status outputs for internal MSYNC state machine.
• Architecture facilitates RAM sharing with other EFEC cores.
• Provides a configurable High BER alarm.
• Provides a single-bit error insertion capability.
• Overall latency of 35us for 40G ports, 140us for 10G ports.

Benefits

• Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
• Xelic offers flexible licensing terms with single use, source code options available.

Deliverables

• Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).