The Xelic 40G Optical Transport Network (OTN) Frame/Lane Alignment Unit Core (XCO23AU/XCO3AU) performs OTL Frame Alignment, Lane Alignment, Lane Deskew, and Lane Rotation, as outlined in G.709 and G.798 specifications with optional scramble and descramble functionality. The XCO23AU core can be configured for 40G or 4x10G operation and the XCO3AU is limited to 40G operation only. Independent Transmit and Receive processors support OTUk signal transport with OTUk AIS insertion and detection capability. Incoming high speed data from optics is timed using recovered clocks and transferred to system clock timing with a data valid scheme for downstream processing. A flexible data bus architecture is used to provide 32 byte transfers for FPGA applications and 16 byte transfers for ASIC implementations. The line-side lane interface supports 4x10G (XCO23AU option) and 40G OTL3.4 while a separate line-side interface is provided to support data to/from a 40G OTU3 SFI interface.
The XCO23AU/XCO3AU Transmit Processor contains a Transmit Controller, Scrambler, OTUk AIS Generator and Lane Rotation block for multichannel parallel interface support. The Transmit Controller uses incoming FAS signaling to enable optional OTUk signal scrambling. For OTL3.4 mode, the logical lane identifier is extracted from the incoming MFAS field and used for Lane Rotation. The transmit processor includes OTUk-AIS/OTL3.4-AIS generation and an optional lane-based test pattern generator.
The XCO23AU/XCO3AU Receive Processor contains an Optical channel Transport Lane (OTL) Frame Aligner, OTL AIS detector, OTUk AIS detector, Lane Aligner with Deskew and Lane Rotation, and OTN frame descrambler. The OTL Frame Aligner performs frame alignment of OTUk frames with configuration options for OOF and LOF algorithm state transitions. The OTL AIS detector monitors incoming lanes for OTL AIS and reports status through internal maskable interrupts. Following frame alignment, incoming lanes are aligned and lane deskew is performed before lane data is block muxed into OTUk frames. OTUk AIS is detected and reported on all incoming lanes when configured for 4 x 10G mode of operation (XCO23AU option). A receive system side clock is used to retime incoming data to a system reference.
The XCO23AU/XCO3AU provides Transmit Processor facility and terminal loopback and Receive Processor facility and terminal loopback modes of operation for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped registers is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO23AU/XCO3AU core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Provides transmit and receive loopback options for diagnostic purposes.
- Includes modes of operation for both 40G OTN and 4 x 10G (XCO23AU option) OTN transport.
- Optional OTU3 line-side interface for interfacing to SFIS.
- Provides optional OTUk/OTL3 AIS insertion.
- Optionally scrambles (1 + x + x3 + x12 + x16) incoming OTUk signals.
- Supports OTU3 lane rotation for OTL3.4 multichannel parallel interfacing.
- Optional OTU3 AIS detection.
- Optional lane based Fixed/PRBS test pattern generation on lane interface.
- Data request, data valid flow control supports push and pull modes.
- Performs OTUk frame alignment with programmable OOF/OOM/OOR and LOF/LOFLANE/LOR/LOL detection.
- Supports OPSMnk_TT functions for OTL 3.4 interface (frame alignment, lane recovery, lane deskew, 16 byte block mux).
- Detects LOS, LOF, LOM, LOFLANE, LOL, LOR, OOF, OOM, OOR conditions with maskable interrupt generation.
- Detects OTL AIS and OTUk-AIS error condition with maskable interrupt generation.
- Supports optional descrambling (1 + x + x3 + x12 + x16) of incoming OTUk signals.
- Configurable SSF, and FAIL outputs.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).