The Xelic 40G OTU3 GFEC (XCO3GFEC) core performs FEC encoding and decoding of OTU4 frames using 16 byte-interleaved RS(255,239) codewords as specified in ITU-T G.709 Interfaces for the optical transport network (OTN). The XCO3GFEC contains independent encoder and decoder functions fully compliant with the G.709 specification and has been through extensive interoperability testing. Corrected errors and uncorrectable codeword detection is provided along with a configurable High BER alarm. Line and system side data is transferred at an OTU3 rate using a 256-bit data bus operating at a nominal frequency of 167.7MHz.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO3GFEC core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.709 specification.
- Contains 7 parity overhead
- Encoder includes single bit error insertion for diagnostic purposes.
- Provides outputs for scrambled line values of corrected ones and corrected zeroes
- Provides corrected symbols and uncorrected codewords outputs.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Overall latency of less than 1us.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).