40nm-G USB 3.0 SuperSpeed PHY

Features

• Fully compliant with USB 3.0 SuperSpeed electrical interface specifications
• PIPE3 interface for ease of integration
• Single or multiple lanes supported
• Complete integrated USB 3.0 PHY and Controller solution available
• Adaptive receive equalization mitigates signal attenuation due to the channel, and crosstalk noise
• Low power transmit driver features programmable transmit amplitude, pre-emphasis, and slew rate
• CMU technology includes fractional synthesis to support spread-spectrum clocking
• All USB 3.0 power saving modes (U0, U1, U2, and U3) are supported for ultra-low power operation
• Extensive testability features including various loopback modes, on-chip pattern generator and checker

Deliverables

• Specification and Integration Manual
• GDSII and Layer Map Files
• Library Exchange Format (LEF) defining size and pin locations
• Verilog PHY Behavioral Model and Testbenches
• Timing Constraint File
• DRC and LVS reports
• Netlist in SPICE format for LVS