This 6 bit ADC IP is implemented in TSMC65NMLP process. It can achieve 5.3125GHZ sampling rate and 2.65GHZ signal bandwidth while consumes only 155mw. ENOB is greater than or equal to 5.5 bit for signals below 1GHZ and 5.2 bit for signals below 2.6GHZ.
This ADC IP includes an AGC(Automatic Gain Control Buffer) in front of the ADC. For AGC input signal amplitude between 150mv to 1.2v, AGCís output can be adjusted to full dynamic range of the ADC by controlling AGCís gain.
A low jitter PLL (RJ<500fs RMS) is also included to provide precise sampling clock for the ADC . This will prevent jittery sampling clock from degrading ADCís performance when ADC is sampling high frequency signal up to 2.65GHZ.
- 6 bit Flash ADC with a single sampling clock from 4.0625GHZ to 5.3125GHZ
- Automatic offset cancellation circuitry
- ENOB>= 5.5 bit (SNR 34.87db) for input signals <= 1GHZ
- ENOB>= 5.2 bit (SNR 33.06db) for input signals <= 2.65GHz
- Built in AGC and Fractional Divider
- Input bandwidth 2.65Ghz
- Programmable input signal amplitude from 150mV to 1.2V (Differential Peak to Peak)
- Excellent power supply noise rejection
- Power 1.2V/2.5V
- Process TSMC 65LP
- Verilog Model
- LEF view
- Timing Libraries
- ATPG Model & Netlist
- GDS Phanton View
- Spice Netlist
- Usage Guide and Documentation
- Integration Review
- Wireless, Wireline, high speed interfaces, AFEs, Modems
Block Diagram of the 6-bit 5.3125GHz Analog To Digital Converter