The 60GHz PLL consists of a quadrature oscillator, a low noise digital phase frequency detector (PFD), a programmable charge pump, programmable A and M counters, and a dual modulus prescaler (P/P + 1). The A (7-bit) and M (8-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A).
Control of all the on-chip registers is achieved via a simple 4-wire interface with 1.2 V compatibility. The device operates with a power supply of 1.2 V.
- 60GHz - 1.2 V operation.
- Quadrature differential outputs
- Selectable charge pump output current options (20uA, 50uA, 100uA and 200uA) offering the capability to efficiently adjust to the PLL dynamics of the targeted application.
- Built-in dual modulus prescaler. Prescaler division ratio :8/9
- Wide-band CMOS LC voltage-controlled oscillator (VCO) that uses a capacitor bank scheme
- Serial input programmable reference counter, swallow counter and programmable counter
- Low phase noise (< -90 dBc/Hz @1MHz offset).
- 100Ohm differential 60GHz output
- 50MHz PLL Channel Resolution
- Physical layout (GDSII) currently available for IBM90nm - can be targeted to other 90nm processes
- Full specification documentation
- Complete simulation test plan and test bench
- Data sheet
- Integration manual