This 65C02 IP core implements a fast, 8-bit microprocessor that executes the same instruction set as the 65C02 microprocessor. The 65C02 is an upgraded version of the popular MOS Technology 6502 8-bit CPU, and was used in many successful products such as the Apple IIc home computer.
The core provides software and hardware interrupts for interfacing external devices. With sixteen addressing modes—including indirect index and zero page—the C65C02 is able to address up to 64KB of external memory with two-byte-long instructions.
The 8-bit arithmetic logic unit can operate on signed and unsigned binary numbers as well as binary-coded decimal numbers.
The C65C02 core offer two instruction to save power by (STP) halt processor and (WAI) wait for interrupt instruction.
The popularity of the 6502 architecture means a significant amount of industry-certified software is ready to use with this core. The core also enables modification of the origi- nal instruction set to better suit new systems and applications.
- Conforms to spec and runs instruction set of original 65C02
- Wait cycles to access slow ROM
- Single clock per cycle, whereas the average cycle number is 2
- Control Unit:
- Maskable interrupt
- Non-maskable interrupt
- Set overflow flag for external numeric processing device
- Synchronization signal for single cycle execution
- Ready state input for DMA interfacing
- Vector Pull output indicates when interrupt vectors are being addressed
- Memory Lock output indicates when instruction perform Read-Modify-Write operation
- 8-bit Instruction Decoder:
- 69 instructions
- 212 operation codes
- 8-bit Arithmetic-Logic Unit:
- Decimal and binary arithmetic operations
- Logical operations
- Logical shift operations
- External Memory Interface:
- Addressing up to 64 KB of: External Program Memory, External Data Memory, External Input/Output space
- 16 addressing modes
- De-multiplexed Address/Data Bus to allow easy connection to memories
- RDY signal for interfacing with slow RAM/ROM modules or DMA
- Power Saving Features:
- Wait for interrupt instruction
- Halt processor instruction
- HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
- An example C65C02 application
- Sophisticated HDL Testbench including external RAM, clock generator, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide