The 7:1 Video SERDES Serializer/Deserializer provides a Channel Link interface to support digital displays. HD video is supported with 6-, 8-, and 10-bit data at a variety of resolutions up to 720p.
Standard deliverables include an Actel-targeted netlist or fully-synthesizable VHDL/Verilog RTL, Simulation models and testbench, Comprehensive user's guide, Timing constraint files, and Technical support.
- 7:1 SERDES Design
- Designed specifically for the Actel ProASIC3 and derivatives
- The 35-bit (7:1 SERDES) uses 1,155 of 24,576 Tiles (5%) of an Actel ProASIC3 A3P1000 Device
- The 28-bit (7:1 SERDES) uses 1,030 of 24,576 Tiles (4%) of an Actel ProASIC3 A3P1000 Device
- The 21-bit (7:1 SERDES) uses 905 of 24,576 Tiles (4%) of an Actel ProASIC3 A3P1000 Device
- Supports Digital Display Interfaces via OpenLDI specification (Channel Link)
- Can be used for 6-, 8-, and 10- bit video data (supports HD video)
- Supports 21-bit parallel data on three LVDS channels
- Supports 28-bit parallel data on four LVDS channels
- Supports 35-bit parallel data on five LVDS channels
- Supports flat-panel LVDS rates to 200 MHz
- Verilog testbench available