The DAC has a current steering architecture with differential current outputs. It uses 4 linear bits and 4 binary bits, all of which are generated from within the current source array. This segmentation results in the excellent static performance and reduced glitch energy at the output. The area has been kept as low as possible by using all 6 layers of metal in an innovative busing arrangement. This ensures parasitics within
the DAC are minimised. The distortion at the output is greatly reduced using a new propriety latch architecture.
The combination of static performance, reduced glitch energy, minimised parasitics and reduced distortion, results in the exceptional dynamic performance measured.
The DAC has been implemented on a standard 90nm low power logic process with 3.3V option. It can be readily ported to any similar manufacturing process. Any activity of this nature can be fully supported.
- 90nm 6 Metal CMOS (No analog options)
- 3.3V and 1.2V power supplies required
- 1 MSPS output update rate
- INL < 1LSB and DNL < 0.5LSB
- Power Dissipation 10mW
- Standby and power down modes
- Total area of 0.10 mm2 (including reference)
- This DAC has been designed to reduce time to market, risk and cost in the development of Analog Front-Ends. A range of supporting IP blocks such as PLLs and A/D converters are also available.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef )
- Timing View (tlf )
- Behavioral Model (VHDL/Verilog)
- Silicon Samples
- DemonstrationEvaluation Board
- Integration Support