An economical, entry-point, fixed-configuration core that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.
The R8051XC-EP provides hardware and software interrupts, an interface for serial communication, two timers, an Intel-compatible interrupt scheme, parallel I/O ports, and a power management unit.
The R8051XC-EP is one of our proven 8051 family of processor cores, which have been successfully implemented in a hundred different customer products. Representative ASIC implementation data shows it to offer competitive performance and area results, requiring for example about 9,000 gates for 350 MHz.
Developed for easy reuse in ASIC and FPGA implementations, the microcode-free design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset. Scan insertion is straightforward.
Features
- * Control Unit
- o Eight-bit instruction decoder for MCS® 51 instruction set
- o Executes instructions with one clock per cycle (versus twelve for standard 80C51) for an average 8x speed up
- * ALU performs 8-bit arithmetic, multiplication and division, and Boolean manipulations
- * 32-bit Input/Output ports
- o Four 8-bit I/O ports
- o Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051
- * Two 16-bit Timer/Counters
- * Interrupt Controller with two priority levels and five sources
- * Internal Data Memory Interface can address up to 256 bytes of Read/Write Data Memory Space
- * External Memory interface
- o Can address up to 8 MB of External Program Memory and up to 8 MB of External Data Memory (when using memory banking)
- o De-multiplexed Address/Data Bus for easy connection to memories
- o Variable length MOVX to access fast/slow RAM or peripherals
- o Wait cycles to access fast/slow ROM
- o Dual data pointer register
- o Program memory write mode
- * Special Function Registers interface services up to 103 External SFRs
- * Power Management Unit – IDLE and STOP modes
- * Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Deliverables
- * HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- * An example implementation with sample system
- * Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- * Simulation script, vectors, and expected results
- * Synthesis script (ASICs) or place and route script (FPGAs)
- * Comprehensive user documentation, including detailed specifications and a system integration guide
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