The Accelerated Display Graphics Engine IP for ASIC & FPGA, is an advanced graphic controller.
The Accelerated Display Graphics Engine IP i is easy to use and to implement. The only external components needed are a memory and a display. The processor may be a separate component or may be embedded with BADGE in the FPGA or ASIC. For analog video, an ADC is needed.
BADGE supports several memory types and this support can be extended to other memories.
BADGE supports several CPU bus types and this support can be extended to other CPU bus types.
- Fully synchronous, synthesizable and technology independent RTL code
- Capable of drawing shapes such as pixels, lines and rectangles
- Capable of drawing text of various fonts, sizes and colors
- Capable of copying, resizing and recolor rectangles – e.g. “BitBlt” and ROP
- Capable of drawing/moving graphical objects – e.g. ”sprites”
- Supports multi-buffered frame memory – which eliminates flicker when graphical objects move
- Supports Analog Video – with external A/D circuit
- Support of alpha blending (2 variants) (New)
- Supports Digital Video – uncompressed (SDI) and compressed (MPEG)
- Anti-aliasing (New)
- Text/Graphics overlay
- Hardware Window – Picture-In-Picture support
- Hardware-cursor support, by making use of sprites
- Programmable frame rate
- Up to 4096 x 4096 pixels display resolution
- Generic color depth up to 24 bits per pixel
- Supports several memory types such as ZBT-SRAM, SDRAM, DDR etc.
- Supports address mapped linear frame buffer or single address command based interface
- Generic data bus width between BADGE and video memory
- Supports many bus types, with a flexible and programmable Bus Interface
- CPU-data bus of 32, 16 and 8-bit supported (8-bit New)
- BADGE has been used with displays such as:
- Sharp display LQ065T9DR51, 400x240 (WQVGA)
- Sharp display LQ057Q3DC12, 320x240 (QVGA) (New)
- Samsung displays LTM150XH-T01, LTM150XH-L04, 1024x768 (XGA)
- AU Optronics A070VW01 7” 800x480 (WVGA)
- AU Optronics 1680x1050 (WSXGA+)
- Supports serial LVDS and parallel LVTTL TFT-interface
- Supports DVI (New)
- Supports Display Power Sequencing
- Supports DE Only Mode, for displays which do not use hsync and vsync inputs
- Support of Portrait mode (New)
- A Test Pattern Generator is included, for debug purpose
- WinCE driver 4.2, 5.0 and 6.0 (CETK approved New)
- Linux driver (accelerated Frame Buffer for Linux New)
- API, for non OS users (New)
- Interfaces: Up to 4096 x 4096 pixels display resolution
- Design size: approx. 1600 Registers in basic configuration
- Implementation example: Xilinx FPGA
- FPGA: Xilinx FPGA Spartan-3 200 or Spartan-6 LX16
- Display memory: 2 SDRAM, 1M x 32 bits each
- Display: 1024 x 768 pixles, 16 bits per pixel, 60 frames per second
- System clock frequency: 100 MHz
- Display clock frequency: 50 MHz
- Other info: The data bus between the FPGA and the video memory is 32 bits wide, which enables 2 simultaneously pixel operations/accesses. Burst access is used to guarantee performance. Multipixel-operations (concurrent access of multiple pixels in the memory) double the performance.
- Implementation example: Altera FPGA
- FPGA: Altera FPGA Cyclone-III
- Display Memory: DDR 48-bit wide
- Display: 1680x1050 pixels (WSXGA+)
- System clock frequency: 100 MHz
- Display clock frequency: 60 Hz
- Other info: The data bus between the FPGA and the video memory is 64 bits wide, which enables 4 simultaneously pixel operations/accesses.
Block Diagram of the Accelerated Display Graphics Engine IP