The Accumulator IP provides LUT and single Xtreme DSP™ slice implementations. The Accumulator module can implement adder-based, subtracter-based, and dynamically configurable adder/subtracter-based accumulators operating on signed or unsigned data.
- Supports fabric implementation inputs ranging from 2 to 256 bits wide
- Supports Xtreme DSP slice implementation with inputs ranging from 2 to 36 or 48 bits wide (varies with device family selection).
- Optional carry output.
- Latency configuration of manual or automatic for maximal speed performance.
- Instantaneous Resource Estimation
- For use with Xilinx CORE Generator™ , Xilinx AccelDSP™ Synthesis Tool, and Xilinx System Generator.