The IPC-Adec-AHB is a fully scalable Address Decoder with a built in remap function to support multiple memory maps. The IPC-Adec-AHB generates separate enable signals for external devices such as FLASH and SRAM, internal memory, and various internal blocks. Datamux select signals are also generated to control which data is muxed onto the AHB data bus. The Address Decoder also detects and reports invalid addresses from the address bus.
The built-in remap logic is controllable through hardware and software. Hardware remap controls allow developers to force a memory map with a jumper connection. This is use-ful during system development and debugging where an in-circuit debugging system is used to boot from volatile memory. Software remap control allows for the system to be remapped on the fly during normal operation. The IPC-Adec-AHB has an AMBA AHB interface.
- ƒ Scalable Address Decoder
- ƒ Hardware and software remap controls
- ƒ Invalid address detection
- ƒ AMBA AHB interface
- The IPC-Adec-AHB package includes fully tested and verified Verilog source. The IPC-Adec-AHB can also be delivered as an FPGA Netlist for Xilinx, Altera and Actel FPGAs.