The CAST application interface (AIF) is designed to provide connection between the FPGA PCIe Hard IP block and SoC local bus. Supported SoC busses are Wishbone, AMBA™ AHB and AMBA™ AXI.
The PCIEXPAIF Altera implementation of the core is compatible with Cyclone IV GX, Arria II GX, Stratix IV GX and Stratix V GX devices.
The PCIEXPAIF Xilinx implementation of the core is compatible with Virtex-5 and Virtex-6 devices.
The PCIEXPAIF integrates a Completer controller and DMA controller with up to eight DMA channels. The functionality of the DMA controller can be extended using the Scatter-Gather controller.
- Altera implementation compatible with Altera Hard IP TLP interface
- Xilinx implementation compatible with Xilinx Hard IP TLP interface
- Wishbone bus specification compliant
- AMBA™ AHB bus specification rev. 2.0 compliant
- AMBA™ AXI bus specification v1.0 compliant
- Configurable FIFO sizes
- Completion controller
- 1-8 independent DMA channels
- Control registers accessible from SoC bus and PCIe bus side
- Interrupt support
- Optional support of other SoC buses
- Scatter-Gather controller extension available
- HDL RTL source or post-synthesis netlist
- Sophisticated HDL Testbench including models of interfaces, and the core
- Simulation scripts, vectors, expected results
- Place and route scripts
- Comprehensive user documentation