The DesignWare® ARC® EM DSP Family, which includes the EM5D and EM7D processors, is optimized for use in low-power embedded applications where DSP performance and low-power consumption is a requirement. Wearable devices in the IoT market need this combination of features to enable optimum device performance and extended battery life.
The EM DSP processors are based on the enhanced ARCv2DSP Instruction Set Architecture (ISA), which adds over 100 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP, vector and single instruction multiple data (SIMD) operations. The new ISA includes support for the following classes of DSP instructions and operations: basic saturating arithmetic, vector unpacking, 32b, 40b, 64b and 72b accumulators, as well as a broad selection of MAC operations including: Vector 16x16, Dual 16x16, Dual 16x8, 32x16, 32x32 and Complex (16+16)x(16+16) multiply accumulate. The EM5D and EM7D processors feature a separate parallel DSP pipeline with the following attributes: full clock-gating support (gated off when inactive), unified low-power, single-cycle 32x32 MUL/MAC unit, square root, divide and FFT butterfly acceleration and a wide 64 + 8-bit accumulator
The new DSP features of the EM5D and EM7D processors are configurable, enabling each instance of the core to be tailored to suit its specific application or DSP workload. For example the data path width can be selected and support for rounding, complex, divide and square root can be enabled or disabled.
The ARC EM DSP family features a balanced 3-stage Harvard architecture pipeline that provides efficient throughput, delivering up to 1.77 DMIPS/MHz and 3.41 CoreMark/MHz*, with power as low as 7 microwatt/MHz. The cores offer excellent real-time control and DSP performance within a footprint as small as 0.03 mm2.
EM DSP processors are highly configurable so that each instance can be tailored to achieve the optimum balance of DSP and RISC performance as well as power and area efficiency. In addition, ARC Processor EXtensions (APEX) technology offers designers the ability to create user-defined instructions, enabling the integration of custom hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required.
To enable easy DSP software development the ARC MetaWare Development Toolkit features a rich DSP software library and the included enhanced C/C++ Compiler supports all of the new DSP functionality and offers industry-leading code density.
The ARC EM5D and EM7D processors support up to 1MB each of instruction and data close coupled memory (CCM). The EM7D adds support for up to 32KB of instruction and data cache.
- ARCv2DSP ISA adds over 100 DSP Instructions
- Fixed point, vector and SIMD DSP processing support
- Power-efficient unified 32x32 MUL/MAC unit
- Highly configurable DSP and processor features for optimal design
- Easy DSP programming support with Metaware C/C++ Compiler
- Feature-rich DSP software library for easy algorithm programming
- Optional hardware divider
- 1.77 DMIPS/MHz and 3.41 CoreMark/MHz
- Support acceleration for APEX Processor Extensions
- JTAG debug interface
- The DesignWare ARC EM5D and EM7D processors are delivered to system designers as Verilog HDL in the ARChitect IP Library
- The HDLis configured and output from the ARChitect IP Configurator tool
- To ensure that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is delivered with the processor cores
- The MetaWare Development Toolkit comes complete with a new DSP C/C++ Compiler specifically supporting all the DSP instructions in the ARCv2DSP ISA
- The MetaWare Toolkit also features a DSP software library supporting a full set of commonly used DSP functions