ARINC 429 Synchronous Transmitter Receiver

Features

• 1 Independent Receivers (Rx) with FIFO
• 1 Independent Transmitter (Tx) with FIFO
• Decoding signals interface type
• 16-Bit Data-bus
• Direct addressing of all Registers
• ARINC 429 Interface : ‘1’ and ‘0’ Lines, RZ code
• Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
• Multi Label Capability
• Parity Control : Odd, Even, No Parity, Interrupt Capability
• Independent Interrupt Request Line for Rx and Tx Functions
• FPGA speed grade operating frequency dependant : system clock up to 70 MHz
• Available in VHDL source code format for ease of customization
• DO254 design, verification and traceability documentation available on request
• Can be customized by Logic Design Solutions

Deliverables

• VHDL Source code
• VHDL Test Bench for behavioural and gate level simulation.
• Data Sheet and Reference GuideUser’s guide : Simulation, Synthesis and Place and Route procedures.
• Constraint File
• DO254 Documentation available on request.